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| RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION DSLAM DSLAM APPS NOTE: SIGNAL INTEGRITY AND TIMING SIMULATION FOR THE VORTEX CHIPSET (S/UNI-DUPLEX, S/UNI-VORTEX, S/UNI-APEX AND S/UNI-ATLAS) Released Issue 1 November 2000 iii PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION REVISION HISTORY Issue No. 1 Issue Date November 2000 Details of Change Document Creation iv PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION CONTENTS 1 INTRODUCTION............................................................................................................... 1 1.1 1.2 1.3 Simulation Goals .................................................................................................. 1 Simulation Tools ................................................................................................... 2 Any-PHY and UL2 Component Placement Configuration.................................... 4 1.3.1 1.3.2 2 S/UNI-APEX - RAM Interface.................................................................. 6 S/UNI-ATLAS - RAM Interface ................................................................ 6 MODELS ........................................................................................................................... 7 2.1 2.2 2.3 IBIS and SBGA Models ........................................................................................ 7 Printed Circuit Board (PCB) Cross-section ........................................................ 10 FR-4 Material...................................................................................................... 12 3 UNIFORM TRANSMISSION LINE EXERCISES ............................................................ 13 3.1 3.2 3.3 3.4 Data Line Simulation .......................................................................................... 13 Clock Line Signal................................................................................................ 17 Serial and Parallel Termination........................................................................... 18 Test Points vs. Edge Distortion........................................................................... 21 4 BUS SIMULATION .......................................................................................................... 23 4.1 4.2 4.3 Bus Complexity................................................................................................... 23 S/UNI-ATLAS and S/UNI-APEX I/O Pads Driving Capability............................. 24 S/UNI-DUPLEX/S/UNI-VORTEX/S/UNI-ATLAS In-line Bus Configuration........ 25 4.3.1 4.3.2 4.4 Many-to-Single In-line Bus Configuration.............................................. 27 Single-to-many In-line Bus Configuration.............................................. 29 Utopia and Any-PHY Dual Bus Offset Configuration.......................................... 34 4.4.1 4.4.2 Many-to-single Dual Offset Bus Simulation........................................... 35 Single-to-many Dual Offset Bus Simulation .......................................... 36 4.5 4.6 4.7 4.8 Utopia and Any-PHY Single Bus Offset Configuration ....................................... 37 Multi-Branch Offset Configuration ...................................................................... 40 S/UNI-APEX to Any-PHY Bus ............................................................................ 41 Clock Distribution Simulation.............................................................................. 43 4.8.1 Clock Transmission Line ....................................................................... 43 v PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 4.8.2 4.8.3 4.8.4 5 Buffer Evaluation ................................................................................... 45 Clamping Diodes Current ...................................................................... 47 Crosstalk and EMI ................................................................................. 49 DATA SHEET DERIVED TIMING .................................................................................... 50 5.1 5.2 5.3 VORTEX Chipset Hold and Setup Time............................................................. 50 S/UNI-APEX I/O Drivers..................................................................................... 52 S/UNI-APEX- pc3b04/pc3t04 Valid Signal Correction........................................ 54 5.3.1 S/UNI-APEX with 40 pF Load ............................................................... 54 6 S/UNI-APEX RAM INTERFACE SIMULATION............................................................... 57 6.1 6.2 6.3 6.4 Example of Component Placement.................................................................... 57 S/UNI-APEX RAM Bus Configuration Examples ............................................... 58 Clock Signal to S/UNI-APEX and RAMs Simulation .......................................... 59 S/UNI-APEX - SSRAM Interface ....................................................................... 60 6.4.1 6.4.2 6.5 4x1MB SSRAM In-line Configuration at 80 MHz................................... 60 4x1MB SSRAM Parallel Configuration at 80 MHz ................................ 61 S/UNI-APEX - SSRAM Timing.......................................................................... 63 6.5.1 6.5.2 6.5.3 6.5.4 S/UNI-APEX - SSRAM Edge Timing .................................................... 63 SSRAM Valid Signal Correction ........................................................... 65 Timing Diagram for 2 x 2 SSRAM Configuration................................... 65 Timing Summary for 2 x 2 SSRAM Configuration................................. 68 6.6 7 S/UNI-APEX - SDRAM Interface....................................................................... 70 S/UNI-ATLAS/ and S/UNI-APEX UTOPIA L2 AND ANY-PHY BUS TIMING................... 76 7.1 7.2 7.3 7.4 S/UNI-ATLAS Timing Correction ........................................................................ 76 UTOPIA L2 Timing with Offset Configuration .................................................... 77 Clock Propagation Timing in Offset Configuration ............................................. 79 S/UNI-APEX Timing ........................................................................................... 82 7.4.1 7.4.2 S/UNI-APEX Timing Correction............................................................. 82 S/UNI-APEX Driving Offset Bus with Multiple Termination ................... 83 8 VORTEX CHIPSET SIMULATION SUMMARY............................................................... 88 8.1 Simulation Tools ................................................................................................. 88 vi PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 8.2 8.3 8.4 8.5 8.6 8.7 9 10 In-line Configuration ........................................................................................... 88 Offset Configuration............................................................................................ 90 S/UNI-APEX-RAM Interface............................................................................... 91 Clock Signal Integrity.......................................................................................... 91 Bus Timing.......................................................................................................... 92 Future Simulations ............................................................................................. 93 DISCLAIMER................................................................................................................... 94 GLOSSARY..................................................................................................................... 95 vii PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION LIST OF FIGURES FIGURE 1. DSLAM Core Card Architecture .............................................................. 1 FIGURE 2. Superimposed Curves from HyperLynx and SpecctraQuest Simulations.3 FIGURE 3. Component Placements .......................................................................... 5 FIGURE 4. S/UNI-APEX-RAM Configuration ............................................................ 6 FIGURE 5. SBGA Package Electrical Model ............................................................. 8 FIGURE 6. Simplified Electrical Circuit for SBGA Package and IBIS Model ............. 9 FIGURE 7. PCB Cross-section ................................................................................ 11 FIGURE 8. PCB Bus Connections........................................................................... 11 FIGURE 9. I/O Pad Output Signal Transition........................................................... 13 FIGURE 10. Unterminated Transmission Line Simulation......................................... 14 FIGURE 11. Output loaded with 50 ohm. .................................................................. 15 FIGURE 12. Clock Simulation with Unterminated Line.............................................. 17 FIGURE 13. Line Termination Model ......................................................................... 18 FIGURE 14. Simulated Signal vs. Serial Termination................................................ 20 FIGURE 15. Simulated Signal at Different Test Points .............................................. 22 FIGURE 16. Example of VORTEX Chipset Bus Lines .............................................. 23 FIGURE 17. )S/UNI-APEX S/UNI-ATLAS I/O Pads................................................... 24 FIGURE 18. In-line Bus Configuration ....................................................................... 26 FIGURE 19. In-line Component Placement Simulation ............................................. 27 FIGURE 20. S/UNI-VORTEX-10 to S/UNI-ATLAS-2 vs. Serial Resistor ................... 28 FIGURE 21. Simulation with S/UNI-ATLAS Driving In-line Bus................................. 29 FIGURE 22. S/UNI-ATLAS to Bus In-line with Termination Resistors ....................... 30 FIGURE 23. S/UNI-APEX to Bus In-line with Termination Resistors......................... 32 FIGURE 24. S/UNI-ATLAS Driving Dual-branch Bus ................................................ 33 FIGURE 25. Offset Bus Configuration ....................................................................... 34 FIGURE 26. Receive Data Offset Bus Signal Simulation .......................................... 35 FIGURE 27. S/UNI-DUPLEX to S/UNI-ATLAS vs. Termination Resistor................... 36 FIGURE 28. One-to-many in Dual Bus Offset Configuration.................................... 37 FIGURE 29. Single Bus Offset Component Placement............................................. 38 viii PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 30. S/UNI-ATLAS in a Single Bus Offset Configuration .............................. 39 FIGURE 31. S/UNI-ATLAS in Crow-feet Configuration ............................................. 40 FIGURE 32. S/UNI-APEX to Bus Simulation............................................................. 41 FIGURE 33. S/UNI-APEX to Any-PHY bus in Crow-feet Configuration .................... 42 FIGURE 34. Clock Distribution Simulation................................................................. 44 FIGURE 35. Clock signal at A vs. Thevenin Termination........................................... 45 FIGURE 36. Clock vs. Line Driver Type on Unterminated Line ................................. 46 FIGURE 37. Clock Line Current................................................................................. 47 FIGURE 38. Clock Line Current................................................................................. 48 FIGURE 39. VORTEX Chipset Data Sheet Timing ................................................... 50 FIGURE 40. VORTEX Chipset Data Sheet Timing.................................................... 51 FIGURE 41. S/UNI-APEX IBIS-typical with 50 ohm Load ........................................ 52 FIGURE 42. S/UNI-APEX pc3b04 loaded with 40 pF................................................ 53 FIGURE 43. S/UNI-APEX I/O pc3b04, fast-strong with 40 pF and no load............... 53 FIGURE 44. Propagation Delay for pc3b04 IBIS weak/slow with 40 pF ................... 54 FIGURE 45. Propagation Delay for pc3b04 IBIS fast-strong with 40 pF ................... 55 FIGURE 46. DSLAM Chipset Placement................................................................... 57 FIGURE 47. Example of S/UNI-APEX Interface to SSRAM and SDRAM................. 58 FIGURE 48. Clock Simulation at 80 MHz .................................................................. 59 FIGURE 49. Address Bus Simulation for 16MB SSRAM at 80 MHz ......................... 60 FIGURE 50. ADDRESS to SSRAM ........................................................................... 61 FIGURE 51. DATA from S/UNI-APEX to SSRAM ...................................................... 62 FIGURE 52. DATA from SSRAM to S/UNI-APEX ...................................................... 62 FIGURE 53. ADDRESS to SSRAM, strong/fast, weak/slow...................................... 63 FIGURE 54. DATA from SSRAM-3 at the S/UNI-APEX............................................. 64 FIGURE 55. DATA from SSRAM-1 at the S/UNI-APEX............................................. 64 FIGURE 56. DATA at SSRAM slow-weak and fast-strong with 22 ohm .................... 64 FIGURE 57. SSRAM DATA output IBIS-weak/slow with 30 pF/50 ohm .................... 65 FIGURE 58. S/UNI-APEX to SSRAM-1 with IBIS slow-weak at 80 MHz .................. 66 FIGURE 59. S/UNI-APEX to SSRAM-1 with IBIS Fast-strong at 80 MHz................. 67 FIGURE 60. Timing Summary for SSRAM-1 with IBIS slow - fast ............................ 68 ix PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 61. Waveforms at S/UNI-APEX at 80 MHz ................................................. 69 FIGURE 62. Waveforms at ZBT SSRAM at 80 MHz ................................................. 70 FIGURE 63. ADDRESS to SDRAM ........................................................................... 71 FIGURE 64. DATA to/from SDRAM ........................................................................... 72 FIGURE 65. Waveforms at SDRAM at 80 MHz......................................................... 73 FIGURE 66. Waveforms at SDRAM at 80 MHz......................................................... 74 FIGURE 67. Waveforms at the S/UNI-APEX at 80 MHz ........................................... 75 FIGURE 68. Adjusted Propagation Delay for pbct12 IBIS Typical............................. 76 FIGURE 69. Modified In-line Configuration and Edge Timing ................................... 77 FIGURE 70. In-line Configuration and Edge Timing .................................................. 78 FIGURE 71. CLOCK Propagation Delays with Offset Configuration ......................... 79 FIGURE 72. UTOPIA L2 Bus "typical" ADDRESS and DATA at 52MHz.................... 80 FIGURE 73. DATA and Clock Edge Distortion.......................................................... 81 FIGURE 74. Propagation Delay for pc3b04 IBIS slow-weak with 80 pF ................... 83 FIGURE 75. Edge Distortion Delay............................................................................ 84 FIGURE 76. Any-PHY Bus Timing Simulation at 52 MHz ......................................... 85 x PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION REFERENCES 1. 2. 3. 4. Lee W. Ritchey, "High Speed PCB Design and System Design", Speeding Edge, July 1998 Montrose, Mark I., "Printed Circuit Board Design Techniques for EMC Compliance", IEEE Press, 1996. PCI Industrial Computers manufacturers Group (PICMG) "CompactPCI Specification", PICMG 2.0 R2.1, September 2, 1997. PMC-Sierra Inc., PMC-1990815, "DSLAM Reference Design: Core Card", Issue 3, September 2000 xi PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION Blank page xii PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 1 INTRODUCTION This simulation document for the Vortex Chipset describes: * signal integrity and timing simulation for the PMC-Sierra VORTEX chipset. The VORTEX chipset consists of the S/UNI-APEX, S/UNI-VORTEX, S/UNI-DUPLEX, and S/UNI-ATLAS. the proposed bus configurations and simulation results that apply to the Utopia Level-2 and Any-PHY buses with clock at a 52 MHz and the S/UNIAPEX bus to the SSRAM and SDRAM with clock at 80 MHz. * The simulations are, in general, a paper-design only, without verification on the existing board. FIGURE 1 shows the DSLAM Reference Design architecture block diagram (specific to this simulation document), which includes ten S/UNI-VORTEX devices, one S/UNI-DUPLEX device, one S/UNI-APEX device, and one S/UNIATLAS device. FIGURE 1. Any-PHY, Transmitted Data Loop Any-PHY TX DSLAM Core Card Architecture Utopia L2, Received Data VORTEX 1 WAN Any-PHY RX UL1 Ingress Out Ingress In Policing APEX OAM Cells Loop Any-PHY RX UL2 VORTEX 2 ATLAS Egress In Egress Out DUPLEX WAN Any-PHY TX VORTEX 10 SSRAM context SDRAM cell buffer SSRAM VC table Utopia L2 1.1 Simulation Goals This simulation project was instigated for these purposes: * to address PMC-Sierra's customer needs for a pre-layout bus simulation * to simulate multiple S/UNI-VORTEX/S/UNI-APEX/S/UNI-ATLAS bus * to simulate 80 MHz RAM interface at S/UNI-APEX. 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION The following signal integrity and timing were simulated: * bus signal integrity in the Received Data Utopia L2 direction * * * * bus signal integrity in the Transmit Data Any-PHY direction bus signal integrity on S/UNI-APEX-RAM interfaces clock signal integrity clock/data/address timing. The following items were excluded from simulation: bus lines crosstalk, clock line crosstalk, electromagnetic interference (EMI), simultaneous switching noise, and power and ground noise. Time constraints, lack of simulation tools, and lack of noise models prevented the inclusion of those disturbances in this simulation project. Any source of interference may have significant magnitude. To help build a board with better signal integrity, we recommend: * using a proper layout (with ground and power planes at minimum proximity working as low inductance capacitors) * decoupling/coupling on power rails, integral copper planes without cutouts * minimizing ground and power loops, avoiding long parallel runs of digital traces * reducing back-reflections. The signal integrity simulations and timing diagrams are presented later in this document. 1.2 Simulation Tools For signal integrity simulation, two types of CAD tools were evaluated for this project: * * UNIX-based SpecctraQuest by Cadence PC-based (Win95/98/NT) LineSim by HyperLynx. For bus timing, TimingDesigner - Professional 32 by the Chronology Corporation was used. The first CAD simulation tool evaluated was the UNIX-based SpecctraQuest. The SpecctraQuest simulation began with a simplified board layout. That sets automatically trace impedance, calculated from board stack and additional parameter set manually. A limited number of components from the library was later imported. When the saved program was opened, the previous session components were moved and the connections (wiring) were overlapped, causing some confusion. The on-screen, displayed simulation results (graphs) can be 2 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION saved only as a PostScript file and could not be inserted directly into this document. The GSview (Ghostview) application software was used to convert PostScript into a bitmap file. The second CAD simulation tool evaluated was the PC-based HyperLynx LineSim. The installation was typical for Windows-based applications. A serverbased license allowed for key-less work. The learning curve was shorter than for SpecctraQuest. The pre-layout LineSim simulation tool opened with a fixed matrix of non-active connections and input/output devices. Clicking the element activated it. Typing in data set the parameters, and later copying-and-pasting sped up the procedure. The fixed matrix of components limited the flexibility of the simulation tool. When exiting, this version of the HyperLynx tool did not save the setup properly. Each time the tool is opened, some adjustments are required. There are other minor deficiencies in this simulation tool that are not detailed in this document. The same circuit was entered in both CAD tools and was simulated. FIGURE 2 shows the signal simulation result curves, which are superimposed using the bitmap editor. FIGURE 2. Superimposed Curves from HyperLynx and SpecctraQuest Simulations. HyperLynx Show Previous Waveform = YES SpecctraQuest Both - SpecctraQuest and HyperLinx 3 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION In general, both curves have a very similar shape. The most visible discrepancies show up on the highest overshoot peak, where falling slopes are offset. The differences are also visible in the below-zero voltage area (logic "0"), where HyperLynx has an output of sharp-shaped curves. Technical literature reports that CAD tools may simulate the same circuit with slightly different results. A reason may be a difference in the impedance calculation and the clamping diodes action, which is addressed later in this document. CONCLUSION: The simulation done with relatively advanced tools presents similar results, then it may be trustful to use those tools to predict real circuit behavior. In other words, pre-layout simulation may lead to better designs, may be cost-efficient, and may provide a faster time-to-market cycle. However, it is a must to verify simulation results by taking an oscilloscope measurement on the real board, and if needed, to adjust the termination resistors and layout. Proper oscilloscope measurement techniques are critical in gathering data. NOTE 1. This simulation document contains mostly graphical results of the tryand-error simulations that have been executed while working on the project. All signal integrity simulations, shown later in this document, refer to the HyperLynx LineSim tool only. Timing simulations are done with Timing Designer. NOTE 2: Technical documents stipulate that signal edge distortion cause data corruption in digital circuits, therefore, we put effort to investigate techniques controlling signal integrity. This document, in a large portion, shows hands-on exercises with simulation tools attempting signal edge control. 1.3 Any-PHY and UL2 Component Placement Configuration Two different S/UNI-VORTEX/S/UNI-DUPLEX layout configurations were evaluated: * * the in-line bus placement the offset bus placement. The in-line configuration with ten S/UNI-VORTEX devices and one S/UNIDUPLEX device extends to about 411mm (17.4 inches), which does not fit onto a 6U high board (standard height of the cPCI shelf card). Therefore, a narrower configuration was used as well. FIGURE 3 shows the block diagram with the in-line and offset configurations. This in-line configuration has two subsets of the S/UNI-ATLAS/S/UNI-APEX connections, marked 1 and 2. 4 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 3. VORTEX 10 Component Placements VORTEX 5 VORTEX 1 DUPLEX In-line; 1 active and 10 tri-stated outputs Controlled impedance bus (~50ohm) 411 mm 17.4" 1 ATLAS/ APEX 2 ATLAS/ APEX ATLAS/APEX, simulated at two different positions In-line Configuration VORTEX 9 VORTEX 1 Offset-placement; 1 active and 10 tristated outputs Controlled impedance bus (~50ohm) VORTEX 10 DUPLEX 207 mm 8.2" 1 ATLAS/ APEX ATLAS/APEX Offset Configuration The figure shows the Receive Data bus (Utopia L2) direction (with S/UNIDUPLEX included). Similar configurations are simulated in the Transmit Data (Any-PHY) bus direction (with the S/UNI-DUPLEX disconnected). The offset placement configuration may allow fitting components onto a 6U high board. The total length of the S/UNI-VORTEX/S/UNI-DUPLEX assembly is estimated at about 8.2 inch (207mm). More about spacing and dimensions for each component placement is shown later in this document. 5 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 1.3.1 S/UNI-APEX - RAM Interface FIGURE 4 shows the S/UNI-APEX - NBT SSRAM and S/UNI-APEX - SDRAM configuration. FIGURE 4. SSRAM, 119 PBGA SSRAM 7 SSRAM 5 SSRAM 3 SSRAM 1 SSRAM 8 SSRAM 6 SSRAM 4 SSRAM 2 S/UNI-APEX-RAM Configuration SSRAM, 119 PBGA SSRAM 4 SSRAM 3 SSRAM 2 SSRAM 1 CLOCK SSRAM 3 SSRAM 1 SSRAM 4 SSRAM 2 72-bit DATA 1 Mbyte SSRAM SSRAM 1 CLOCK APEX APEX APEX CLOCK APEX SDRAM 1 SDRAM 2 SDRAM 1 SDRAM 2 SDRAM 1 SDRAM 2 SDRAM 1 A B C D The progress in RAM size has made the first two configurations obsolete. Some RAM manufacturers announced the 72-bit wide DATA interface in a single chip with 1 Mbyte size. The Core Card Reference Design uses two SSRAM chips similar to configuration C above, with SSRAM1 and SSRAM2 only. 1.3.2 S/UNI-ATLAS - RAM Interface The S/UNI-ATLAS - SSRAM interface is not evaluated in this document, as it is relatively slower (50 MHz) and works without problems on other reference design boards. 6 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE SDRAM 2 CLOCK RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 2 2.1 MODELS IBIS and SBGA Models The semiconductor industry provides Input/Output Buffer Information Specification (IBIS) models for I/O pads with IBIS versions 1.1 to 2.1 (2.1 is ANSI/EIA-656 Approved, Dec. 1995). The version 3.2 is currently available on the Internet (3Q 2000). To obtain more information on the version 3.2, go to: http://www.vhdl.org/pub/ibis/ver3.2/ver3_2.txt This simulation document is based on the IBIS 2.1 standard. As of publication of this document, the I/O pads used for the simulation are limited to the following types (based on the PMC-Sierra PM-3350_ED2 and S/UNI-APEX-testchip): - input - output - i/o - i/o pic pob12 pc3t02 pc3b04 S/UNI-VORTEX, S/UNI-DUPLEX and S/UNI-ATLAS S/UNI-VORTEX, S/UNI-DUPLEX and S/UNI-ATLAS S/UNI-APEX S/UNI-APEX The pads have the corresponding IBIS models available in the PMC-Sierra IBIS library. However, this simulation project requires some component values to be modified for the 304-SBGA and 156-PBGA packages, adding or increasing parasitic components (package inductance, capacitance and resistance). The PMC-Sierra IBIS model is created with elements obtained using the following techniques: SPICE model for the silicon I/O pad to derive parallel capacitance C_comp, and data transition speed on positive and negative edges into a 50 ohm load expressed as dV/dt. DC current measurement to determine internal DC resistance and characterize clamping diodes. The current flowing through the clamping diodes is limited to 200 mA, and linearly extrapolated above. parasitic resistance, inductance, and capacitance (RLC), derived from the SBGA package manufacturer's electrical model (AMKOR Technology), which includes wire-bonding wire and copper traces on the BGA printed circuit board; - - The IBIS standard describes the basics of the recommended measurement techniques and the format of the text file required for creating the IBIS models. 7 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION The complete BGA package model includes the first, second, and third order components. The first order elements for the wire and trace are: inductance, capacitance, and resistance. The second and third order components are: mutual inductance and mutual capacitance to the neighboring pads. FIGURE 5 shows the BGA package cross-section and electrical model. FIGURE 5. SBGA Package Electrical Model Semiconductor Wire L13/2 Lwire L11/2 R11/2 C11 R11/2 Lwire Rwire L11/2 L12/2 C12 PCB L13/2 L11/2 C13 L12/2 Rwire R11/2 C11 R11/2 C12 C13 L11/2 L12/2 R11/2 Lwire Rwire L11/2 L13/2 C11 L11/2 L13/2 R11/2 The electrical model can be as complex as presented in the figure above. The model includes a T-configured third order filter with mutual inductance and capacitance to the first adjacent and second adjacent traces. The mutual components introduce cross-talk from the adjacent data/clock BGA connections. The complexity of the complete BGA model cannot be reflected in the IBIS 2.1 model. A simplified electrical circuit was created and is shown in FIGURE 6 below. The mutual L12/13 and C12/13 components are included into L_pin and C_pin. The R_pin represents total DC resistance of the wire and trace. The inductance of the Vcc and GND planes is omitted for this model. The value, shown in the SBGA package data sheets, is approximately L_gnd/L_vcc = 0.1nH. The value is at least one order smaller than the L_pin. The significance of the L_gnd/L_vcc may be observed, when crosstalk from multiple switching I/O pads into a quiet I/O pad is simulated, but this topic goes beyond the scope of this document. FIGURE 6 shows a simplified electrical circuit for the SBGA package and IBIS model. 8 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 6. Silicon Simplified Electrical Circuit for SBGA Package and IBIS Model BGA package, including wire and trace PCB 3.3V L_vcc=0 I/O pad L_pin C_comp GND L_gnd=0 R_pin C_pin SBGA Vcc solder ball SBGA I/O solder ball SBGA GND solder ball TABLE 1 shows the component values for the BGA and IBIS models. TABLE 1. SBGA-304 Electrical and IBIS Models Data SBGA Electrical Model Inductance [nH] L11 Capacitance [pF] C11 t+w 7.2 2.4 L12 Long Short L13 Long Short 0.8 0.6 1.9 1.0 C13 0.03 0.02 IBIS Model L_pin C_pin R_pin C_comp Typ/min/max Resistance [m] R11 Pkg 304 SBGA Size [mm] Body: 31 x 31. Die size: 12.5 x 12.5. Trace Long Short trace trace t+w 1.19 0.45 C12 0.23 0.16 trace t+w 300 160 Pkg 304 SBGA Trace Long Short 8.38 3.53 1.62 0.72 300 160 5.0/4.0/7.0 5.0/4.0/7.0 9 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION The "short" stands for the center I/O pad with the shortest wire and trace length. The "long" stands for the corner I/O pad with the longest connections. The IBIS model requires entering the appropriate data for each pin length. However, some model creators shortcut that process, and all pads have the same parasitic values. Designers are encouraged to exercise effects of different wire bonding and trace length. TABLE 2 shows the component values for the 304-SBGA and 156-PBGA models. TABLE 2. PBGA-156 Electrical and IBIS Models Data PBGA Electrical Model Inductance [nH] Capacitance [pF] C11 t+w 5.86 4.65 L12 C12 1.1 1.0 L13 Long Short 1.0 0.9 C13 0.13 0.08 IBIS Model L_pin C_pin R_pin C_comp Typ/min/max Resistance [m] R11 Body Pkg 156 PBGA [mm] Body 15x15 Trace Long Short trace L11 trace t+w 0.9 0.45 trace t+w 180 140 Die size 5.6x 5.6 Long Short 0.14 0.10 Pkg 156 PBGA Body - Trace Long Short 6.61 5.43 1.37 0.74 180 140 5.0/4.0/7.0 5.0/4.0/7.0 The length of wire and trace has a significant effect on the electrical and IBIS model parameters, which may vary from 10% to 100%. For example, Table 2 shows the C_pin on the short pin is about 40% lower than on the long one. 2.2 Printed Circuit Board (PCB) Cross-section The simulation was done for the 10-layer PCB. FIGURE 7 shows layers of copper and dielectric. Copper thickness is expressed as 1 oz for the internal traces, and 1.5 oz for the top and bottom layers (shown as 1 and 10). 10 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 7. Copper 0.5+1.0 oz PCB Cross-section Layer spacing 5 7 3 7 3 7 7 5 7 Layer name 1 2 +3.3V GND 5 6 +3.3V GND 9 10 Trace impedance 81 56 . . 49 49 . . 56 81 1.0 oz 5 5 5 0.5+1.0 oz Trace width The trace impedance is calculated by the HyperLynx program, and shown in the right-most column in the figure above. FIGURE 8 shows a cross-section of the printed circuit board connections, between devices attached to the bus. The copper connections simulated with the LineSim are highlighted. FIGURE 8. BGA 81 56 49 Main Bus Line PCB Bus Connections BGA IBIS Model Connection VIAs Stub VIAs LineSim Model Connection VIAs IBIS Model The BGA-to-BGA connection consists of three types of copper traces: 81 ohm, 56 ohm, and 49 ohm. The signal path includes four VIAs that connect the shorter traces to the main 49 ohm bus. The central VIA connect stubs to other S/UNIVORTEX/S/UNI-DUPLEX devices on the bus. It is believed that VIAs have a negligible effect on signal integrity for edges slower than 0.5 ns and are, therefore, omitted in the simulations. 11 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 2.3 FR-4 Material A variation was found in the literature on the dielectric constant r of the FR-4 5. The r value depends on the ratio of the glass-to-resin content, and it may depend on the measuring techniques and other factors. The effect of that variation is suppressed as the r is used in equations as a square root and also as one of the many factors in the sum. A value of r =4.5 was chosen for the HyperLynx simulation and for the equation below. The equation calculates impedance of a buried microstrip line, shown as layers 2 and 9 in FIGURE 7: Heigth Thicknes 1.0676 Zo = 43.037 Width + 5.048 Width + = 49.8ohm. 1.09 r glass-resin material. The r value was quoted to be as low as 4.1 and as high as The calculated value differs from the Zo = 56 ohm derived from the HyperLynx tool. (We have not investigated the discrepancy yet.) In general, digital lines are loaded with impedance significantly higher than Zo. Therefore, some impedance discrepancy may not be a significant factor in signal integrity simulations. In general, the r should be decreased for simulations with higher clock speed. 12 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 3 UNIFORM TRANSMISSION LINE EXERCISES The following three sections briefly introduce the simulated behavior of a transmission line passing signal with edge rise time, which is shorter than the transition electrical length (TEL) for that line. TEL is the length of trace that the electromagnetic wave travels during the edge transition time. 3.1 Data Line Simulation FIGURE 9 shows the LineSim that presents simulation results from two exercises conducted in an oscilloscope-like view. FIGURE 9. A 3.500 volts I/O Pad Output Signal Transition B 3.500 volts VORTEX output unloaded C 3.500 volts VORTEX output unloaded VORTEX output loaded with 50ohm to GND 500 mV/div 500 mV/div 500 mV/div 100 psec/div 5 nsec/div 0.0 volts 100 psec/div 0.0 volts 0.0 volts -1.000 volts 0.000ns 50.000ns -1.000 volts 0.000ns 1.000ns -1.000 volts 0.000ns 1.000ns Delta Voltage = 1.97 V, Delta Time = 344 ps Delta Voltage = 1.21 V, Delta Time = 0.24 ns The first exercise was simulation with the I/O pad driving two options: no load and a 50-ohm load. Graphs A and B show an unterminated output with the time base at 5 ns/div and 100 ps/div. Graph C shows a rising edge at 50 ohm resistor to ground. The IBIS text file includes rise and fall time for the pbct12 silicone pad, which is calculated with the SPICE model. Text file shows edge speed at 1.23 V/1.60x10-10 sec, which can be converted to a slew rate of 7.5 V/ns. The slew rate derived from graph C in FIGURE 9 was calculated at 5.04 V/ns. The lower slew rate was most likely due to the LRC elements in the IBIS model, which are not included in the SPICE model. The "monotonic edge" expression throughout this document means monotonic increasing or monotonic decreasing edge, excluding dv/dt = 0. The "nonmonotonic" includes flat shelf and "bumps" dv/dt = 0 or dv/dt > 0 on the same edge in 0.8 V to 2 V region. The next exercise was simulation with the I/O pad driving the long transmission line. The signal was probed at two different configurations. The first configuration probed the rising edge at a BGA pin with an unterminated transmission line at 0, 4 and 8 inches long. The second configuration probed the signal at the end of the four-inch long transmission line section with an additional 13 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION line attached at zero, four, and eight inch of length (shown as 0", 4" and 8"). FIGURE 10 shows the simulation results. FIGURE 10. Unterminated Transmission Line Simulation VORTEX I/O pad Unterminated transmission line 0" 4" 8" VORTEX I/O pad Unterminated transmission line 0" 4" 8" 4" A Rising edge with transmission lines 0/4"/8" 3.5V 7.0V B Overshoot on logic "1" and "0" at the end of 4" transmission line 3.5V C Rising edge at 4" from I/O pad with transmission lines attached 0/4"/8". 3.5V D Data transitions with 8" unterminated line 0" 2.0 V 4" 8" 4.17 V 2.0V 0" 4" 8" 2.0V 0.8V 0.0 volts 0.0 V -1.45 V 0 500 psec/div 500 mV/div Delta Time = 1.13 ns 5ns 0.000ns 5 nsec/div 1 V/div 50ns 0.8V 0.0 V 0.8V 0.0 V -1.0V -1.0V 0 500 psec/div 500 mV/div Delta Time = 1.1 ns 5ns -1.0V 0 5 nsec/div 500 mV/div 50ns Delta Voltage = 5.62 V, Delta Time = 19.1 ns Graphs A and C show the rising edges that have a similar character. The rising edges marked 0" are very monotonic because no transmission line is attached after the probe point. With attached transmission line length of 4" and 8" a flat "shelf" is visible. The phenomenon occurs when a fast edge enters the transmission line, and there is no information yet on what is at the end of the line. Some hundreds of picoseconds later, the wave returns from the unterminated line end and adds up to the voltage level. A voltage divider consisting of internal I/O pad impedance and Zo determines the "shelf" level. Termination at the end of the line has no effect on the shelf voltage level. It is important to notice that the preceding transmission line has little effect on the signal edge. Graphs A and C look similar from 0 V to 3.0 V. The top of the square wave may have more ripples with a longer line overall. The flat region of the edge is about 0.76ns long for the 4" line and about 2.1ns long for the 8" line. Graph D shows the 8" wave with a different time-base of 5ns/div. The flat section is visible on the rising and falling edges of the waveform. Technical literature reports that the "shelf" on data signals may produce soft errors in digital circuits, which may happen a few times a minute or a few times a day, and are difficult to trace. To limit the flat region to about 150 ps, the unterminated transmission line should not exceed 2.5 inches with the transition speed of the pbct12 I/O pad. In general, the flat region on the signal edge(s) functions based on these two factors: 14 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION * * speed of the edge itself length of the transmission line. The faster the edge, the shorter the transmission line can be attached without signal deterioration. This implies "shrinking" the package size of the integrated circuit and minimizing the bus length. A micro BGA package allows placing components with shorter bus lines maintaining better signal integrity. Graphs B and D in FIGURE 10 show a significant voltage overshoot. The negative peak goes to about -1.45 V (and can go much lower as shown in the following sections). This voltage level drives the current through the clamping diodes at the I/O pad. A report indicated that the overshoot waveform that terminated at a pad was causing data corruption into the adjacent pads, which were connected to "clean" waveforms. This type of interference may not be detectable with an oscilloscope, as this phenomenon is internal to the silicon and may not show up on the external pin. In this case, troubleshooting is difficult, and requires an experienced and knowledgeable engineering staff chasing rare occurrences, when unrelated data/clock I/O pads are interfered with overshot signal connected to another pin. The question arises - why not to terminate transmission line with 50 ohm resistor and prevent back reflections? The following FIGURE 11 shows the answer. The output with pob12 I/O pad was loaded with a 50 ohm resistor and simulated with the LineSim. FIGURE 11. Output loaded with 50 ohm. Output with pob12 I/O pad +3.3V 50ohm 50ohm GND 50ohm +1.2V A B C I/O loaded with 50ohm to 1.2V 3.5V I/O loaded with 50ohm to GND 3.500 volts 3.5V I/O loaded with 50ohm to 3.3V 2.0V 2.0V 2.0V 0.8V 0.0 0.8V 0.0 0.8V 0.0 -1.0V 0.000ns 5 nsec/div 500 mV/div 50.000ns -1.0V -1.0V 0 5 nsec/div 500 mV/div 50.000ns 0 5 nsec/div 500 mV/div 50.000ns 15 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION Graph A shows a signal with a 50 ohm load terminated to ground. Graph B shows a wave with a 50 ohm resistor terminated to +3.3 V. Graph C shows a signal with a 50 ohm load terminated to 1.2 V. The logic transition voltage for the 3.3 V devices (S/UNI-VORTEX, S/UNIDUPLEX, S/UNI-ATLAS, and S/UNI-APEX) is specified at 0.8 V to 2.0 V. The logic high and low should have the appropriate voltage margin above and below those threshold levels respectively. The voltage margin is needed to prevent data corruption from ground bounces, power noise, cross-talk, EMI, timing inaccuracy and other signal deficiencies. Graph A shows logic high at 2.0 V, providing no voltage margin for the input pad. Graph B shows logic low at 1.0 V, which is above the 0.8 V threshold. Graph C shows margins on logic low and high at about 500 mV. The margin is not enough to prevent data corruption in real circuits. The signal compression with the 50 ohm load is due to internal resistance of the MOSFET transistors at the I/O pad. This resistance is different for P and N transistors, creating an asymmetry with termination to ground and 3.3 V. The driver needs to source 60 mA to maintain the logic high at 3.0 V with a 50 ohm resistor connected to ground. The pob12 I/O pad cannot deliver this current. The "C" circuit requires additional 1.2 V power rail on the printed circuit board. The noise on this power rail will be coupled into data lines through the 50 ohm resistors. A "quiet" rail is required, which may not be feasible in a noisy digital environment. Regulated power supply and filtering capacitors are needed to maintain this power rail. Also, 50 ohm terminations, to ground or power rail, require a high current at the driver, increasing the total power dissipation in a silicon device. To conclude, the line impedance that matches the parallel termination (about 50 ohm) is not possible with the pob12 I/O pad under investigation. A theoretical solution may be to create transmission lines with a high Zo, for example, 150 ohm. This allows a termination resistor at 150 ohm, and in turn, the I/O pad may provide an adequate driving current to deliver logic high with the appropriate margin. However, such a high-Zo trace will be difficult to design with the 10-layer board. A stripline (layer 5 and 6 in FIGURE 7) at 1 mill (0.001 inch) wide is calculated to have Zo = 74 ohm. The layer 1 line at 1 mill has impedance at Zo = 129 ohm. The 1 mill wide trace is impossible to manufacture for commercial applications. The high-Zo transmission lines require very narrow copper traces manifesting residual inductive impedance due to the skin effect. This may limit the frequency bandwidth, and the edge and clock speed on the transmission line. Also, the 150 ohm line requires higher distance to a ground 16 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION plane, thus increasing crosstalk and EMI. If bus lines are split, the high impedance transmission line would show back-reflections the same way as the low-Zo transmission line. A typical bus layout comprises split bus lines. 3.2 Clock Line Signal The clock signal integrity requires clock edges to be monotonic in the logic signal transition region of 0.8 V to 2.0 V. LineSim was used to simulate the clock signal at 52 MHz with an unterminated transmission line. FIGURE 12 shows the results of this exercise. FIGURE 12. Clock Simulation with Unterminated Line CLOCK=52MHz Unterminated transmission line 5.86" 1.62" 1.62" A I/O output 52MHz clock 3.5V 3.5V I/O output 52MHz clock B C I/O outputs 52MHz clock 3.5V 3.5V D I/O outputs 52MHz clock 2.0V 2.0V 2.0V 2.0V 0.8V 0.0 0.8V 0.0 0.8V 0.0 0.8V 0.0 -1.0V 0 5 nsec/div 500 mV/div Clock edge -1.0V 50ns 5 nsec/div 500 mV/div Clock edge -1.0V 50 ns 5 nsec/div 500 mV/div Clock edge -1.0V 50 ns 5 nsec/div 50ns Clock edge 3.5V 3.5V 3.5V 3.5V 2.0V 2.0V 2.0V 2.0V 0.8V 0.0 0.8V 0.0 0.8V 0.0 0.8V 0.0 -1.0V 0 500 psec/div 5 ns -1.0V 0 500 psec/div -1.0V 5 ns 0ns 500 psec/div 5ns -1.0V 0 500 psec/div 5ns The clock signal is captured using two different time-bases. The upper row shows a multiple clock transition at 5 nsec/div, and the lower row shows a rising edge at 500 psec/div. Points A and B show rising edges that are not suitable for the most bus applications. Note that the "shelf" is not clearly visible on the upper Graph B, which raises the issues of a proper setup of the simulation tools and measurement techniques on real boards. 17 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION Graph C shows a monotonic edge at the probe point located 1.62 inch before the line end. As shown, the clock signal closer to the source has the edges more distorted than the same clock signal at the end of the transmission line. The overshoot and undershoot is significantly higher at the line end. Graph D shows the clock edge is fastest at the line end. If two devices are at some distance from each other and are driven with the same clock line connected in series, some edge skew may be introduced not only by the trace length but also by the edge slope. 3.3 Serial and Parallel Termination This section briefly analyzes signal integrity versus the serial and parallel termination resistors that are attached to the bus. The bus termination mythology implies inserting the serial termination resistors at the beginning of the line, and placing parallel terminations at the signal destination close to the line end. FIGURE 13 shows the termination models. FIGURE 13. Line Termination Model +3.3V Output pad Rt +3.3V Vcc Rt Transmission Line Rs Zo Vt Rt1 Rt2 Rt Zout Ct Rt GND A B C D E F The line terminations shown above can be described briefly as follows: * * * * A - a serial resistor, usually Rs |Zo - Zout| B - a parallel resistor to ground, Rt is usually matching or exceeding Zo. C - a parallel resistor to power (noise from power coupled into data line) D - the Thevenin termination consisting of Rt1 and Rt2 connected to Vcc and GND respectively. Impedance of the parallel resistors matches or exceeds Zo. E - a termination know as the "AC-termination", where high frequency components of the signal edge are terminated with the Rt, and a DC content is blocked by the Ct capacitor. F - a parallel resistor to the power rail at about 1.2 V to 1.5V. The resistor value matches or exceeds Zo. 18 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE * * RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION A recommended line-end termination is the Thevenin circuit, which provides good impedance matching and is not as demanding for the high current drive as the B and C terminations. The F termination requires an additional low noise power rail. All DC coupled parallel terminations decrease the logic voltage swing. The ACtermination targets the near-edge portion of the signal. However, in high-speed designs, the whole signal usually degrades with AC termination, and this type is rarely seen. FIGURE 13, above, presents the termination circuits that apply to the point-topoint transmission line. In a bus environment, stubs and capacitive loads are distributed across lengthy transmission lines, and the classic terminations may not work. It is shown later in this document and measured on a real board, that serial termination at the beginning and parallel termination at the end are not the best solutions in split buses. FIGURE 14 (below) shows a simulation which tries to explore a different placement of a serial termination and signal degradation effects. 19 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 14. Simulated Signal vs. Serial Termination Output with pob12 I/O pad Output with pob12 I/O pad Transmission Line 10" Input 1 Input 2 Rs Rs1 5" Rs2 5" A Signal at 10" line end, no termination, VORTEX driver B C Both columns with Rs2 termination only D I/O pad at 5" with 0.4" stub, no termination I/O pad at 10" with 0.4" stub, no termination 3.5V Row 1 0 ohm 0 1A -1.0V 0ns 5 nsec/div 500 mV/div 50ns This column with Rs1 termination only I/O pad at 5" and 10" with 0.4" stubs, 15 ohm at VORTEX driver 1C I/O pad at 5" with 0.4" stub, 15 ohm after T 1D 3.5V Signal at 10" line end, 15 ohm at VORTEX driver I/O pad at 10" with 0.4" stub, 15 ohm after T Row 2 15 ohm 0 2A -1.0V 0ns 5 nsec/div 500 mV/div 50ns 2B I/O pad at 5" and 10" with 0.4" stubs, 50 ohm at VORTEX driver 2C Rs1 = 0, Rs2 = 15 ohm I/O pad at 5" with 0.4" stub, 50 ohm after T 2D Rs1 = 0, Rs2 = 15 ohm I/O pad at 10" with 0.4" stub, 50 ohm after T 3.5V Signal at 10" line end, 50 ohm at VORTEX driver Row 3 50 ohm 0 3A -1.0V 0ns 5 nsec/div 500 mV/div 50ns 3B 3C Rs1 = 0, Rs2 = 50 ohm 3D Rs1 = 0, Rs2 = 50 ohm Column A in FIGURE 14 shows the signal at the end of the 10-inch long unloaded line. Graph 1A shows strong back-reflections with an unterminated line. Graph 2A shows a 'perfect' logic high, and some overshoot on low with Rs = 15 ohm inserted immediately to the I/O driver. The 3A graph shows an overterminated signal with the serial resistor Rs at 50 ohm. Columns B, C, and D show simulated signals with two devices connected: 20 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION * * Input 1 at 5 inch from the driver Input 2 at the end of the 10 inch line. Column B shows two curves on each graph due to space limitations. The row 2 graph shows a signal at both Inputs 1 and 2, with serial resistor Rs1 = 15 ohm placed immediately to the driver. The signal at Input 1 has a non-monotonic edge in logic transition region 0.8 V to 2.0 V. Graph 3B shows multiple -backreflections on both curves due to over-termination. Columns C and D show simulated signals with serial resistor Rs2 placed at the beginning of the second 5 inch section of the transmission line, and Rs1 = 0 ohm. All four graphs in the lower right corner of FIGURE 14 (2C, 2D, 3C, and 3D) show monotonic edges in the 0.8 V to 2.0 V transition region with low overshoots. The over-terminated line with Rs2 = 50 ohm shown on graph 3C (only Rs2) has relatively the best performance for Input 1 (surprisingly). The double edges in 2B and 3B show propagation delay at both inputs. The above explanation and time consuming data gathering to show that the ruleof-a-thumb placement of the serial resistor, at the beginning of the transmission line, may not be the best solution in a bus configuration. To conclude, the serial termination resistor may improve signal shape if the resistor is placed further in the middle or towards the end of the transmission line. Also, relatively high resistor values (50 ohm +) provide a better termination. 3.4 Test Points vs. Edge Distortion The edge distortion, on a transmission line, may lead to a false conclusion regarding signal integrity and timing when tested at wrong spots. Examples of waveform distortion at different test point locations are shown in FIGURE 15 below. 21 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 15. Simulated Signal at Different Test Points Logic Analyser Oscilloscope YES CLOCK 50 MHz 0.5"_ 12.5 mm Rs 2.0"_ 50 mm 2.0"_ 50 mm 7 pF A B C D E 3.5 V 3.5 V 3.5 V 3.5 V 0.5 V/div 0.5 V/div 0.5 V/div 0.5 V/div 0.0 V -1.0 V 0.0 V -1.0 V 20 ns 0.0 V -1.0 V 0ns 0.0 V -1.0 V 20 ns 0ns 2 ns/div 0ns 2 ns/div 20 ns 2 ns/div 0ns 2 ns/div 20 ns The signal integrity and timing should not be obtained at the beginning or in the middle of a transmission line. Testing waveforms at points A, B, C and D may lead to false conclusions due to significant backreflections. The proper test point is at the transmission line end - E, where the signal shows up without any edge distortion. 22 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 4 BUS SIMULATION This section presents LineSim at work for the pre-layout circuit consisting of 10xS/UNI-VORTEX, 1xS/UNI-DUPLEX, 1xS/UNI-ATLAS, and 1xS/UNI-APEX devices. 4.1 Bus Complexity FIGURE 16 shows the data and clock lines related to the S/UNI-VORTEX/S/UNIDUPLEX interface. Digital lines are grouped into sections with different speed requirements. The bus list includes the Utopia L2 bus (1), the Any-PHY bus (2), the microprocessor interface bus (3), and the optional JTAG bus (5). Clock distribution (4) is also a vital part of the layout, and it is laid out in a point-to-point configuration. The total number of lines in all buses is over 88. FIGURE 16. Example of VORTEX Chipset Bus Lines LVDS DUPLEX/ VORTEX RDAT[15:0] 1 RADR[4:0] RPA, RENB, RSX RSOP, RPRTY TDAT[15:0] 2 TADR[11:0] TPA, TENB, TSX TPRTY 3 D[7:0] A[9:0] CSB, RDB, WRB, ALE, INTB, RSTB uP ATLAS APEX TDO, TDI, TCK, TMS, TRSTB CLOCK 52MHz 4 5 REFCLK JTAG optional 23 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION Each S/UNI-VORTEX/S/UNI-DUPLEX needs three clocks: RCLK, TCLK and REFCLK. RCLK and TCLK can share the same clock signal, and in turn, the total of the two clock traces can be run to each device. The clock lines have to be designed and verified, with the simulation tools and real board oscilloscope measurement to avoid the non-monotonic edges. In some designs clock skew to RCLK and TCLK is necessary - timing simulation is required to optimize circuit. Also, timing skew may be required between different entities connected to the same bus - as shown further in this document. The signal simulation described in this document applies to some of the high-speed bus lines highlighted in FIGURE 16 above. RCLK and TCLK can be up to 52 MHz. The REFCLK is at 1/8 of the LVDS link clock, for example, if the LVDS interface is at 200 Mbs, then the REFCLK is 25 MHz. The fastest clocks are usually running Utopia and Any-PHY buses up to 52 MHz. The interfaces between the S/UNI-APEX and RAMs can be at 80 MHz. The RAM interfaces are not shown in FIGURE 16 and are addressed later in this document. The appropriate layout techniques must be implemented to place all 88 highspeed data bus lines, 22 point-to-point clock lines and termination resistors. At the same time signal integrity with low crosstalk and controlled back-reflections must be maintained. 4.2 S/UNI-ATLAS and S/UNI-APEX I/O Pads Driving Capability The IBIS model for the S/UNI-APEX and S/UNI-ATLAS I/O pads is used in simulation to determine the driving capability. FIGURE 17 shows the simulation plots that are shown together for comparison purposes. FIGURE 17. )S/UNI-APEX S/UNI-ATLAS I/O Pads S/UNI-APEX, pc3b04, S/UNI-ATLAS/DUPLEX/ VORTEX, pbct12, all typical, 50 ohm load to ground S/UNI-APEX, pc3b04, pc3t04, pc3t02, pc3b01, typical, 50ohm load to ground 3.500 V Simulation circuit with I/O pads pbct12, pc3b01, pc3t02, pc3t04, pc3b04 3.5 V APEX pc3b04 ATLAS pbct12 500 mV/div pc3t04, pc3b04 pc3t02 500 mV/div pc3b01 50ohm 0.0 volts 0.0 volts A GND B -1.0 V 0.000ns 500 ps/div V = 1.21 V, T = 0.76 ns 5.000ns C -1.0 V 0.000ns 500 psec/div 5.000ns 24 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION The highest current is delivered by the S/UNI-APEX pc3b04 and pc3t04 I/O pads (0.25u process). The fastest edge is delivered by the S/UNI-ATLAS/S/UNIVORTEX/S/UNI-DUPLEX pbct12 I/O pad (0.35u process). The pc3b04/pc3t04 pads drive the SSRAM Address/Data, Utopia L2 or Any-PHY buses, with ten devices attached to the bus (in this simulation document). The pbct12 pad drives the Utopia L2 bus with eleven devices at the bus. The pc3t02 has an edge speed similar to the pc3b04 with a lower current drive. The pc3t02 pad is used for SSRAM control lines. The S/UNI-APEX pc3b01 pad delivers a significantly lower current and lower speed. This pad drives the WAN site bus between the S/UNI-APEX and the S/UNI-ATLAS. The bus has only two devices connected as a point-to-point configuration. NOTE: All Utopia interfaces are done with the IBIS model set at "typical". The strong/fast and weak/slow IBIS models are used for the SSRAM - S/UNI-APEX interface only. Designers can choose whether to repeat simulations with different IBIS model settings. 4.3 S/UNI-DUPLEX/S/UNI-VORTEX/S/UNI-ATLAS In-line Bus Configuration The DSLAM devices are placed in an in-line configuration, and signal integrity is simulated. FIGURE 18 shows the in-line configuration. 25 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 18. In-line Bus Configuration DUPLEX 10.3 mm 0.4" VORTEX 1 Devices placed with a gap of 0.4" (approx. 1/3 of the 304 SBGA dimension) 304 SBGA package 31x31 mm 1.22x1.22 inch VORTEX 2 Device spacing 41.1 mm and trace 1.62" section length Bus IBIS Model Total assembly length 442 mm 17.4" VORTEX 3 2x via's The main bus trace length 411 mm 16.2" VORTEX 4 IBIS model includes silicon pad, wire bonding and trace on the SBGA package Connction to bus: two vias and copper traces VORTEX 5 50=-=100 Termination VORTEX 6 Input ATLAS LVDS Interfaces VORTEX 7 10.2mm 0.40 APEX APEX not connected in this direction VORTEX 8 70 mm 2.76" VORTEX 9 Output Input VORTEX 10 26 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION The in-line configuration provides a natural data flow with the LVDS interfaces on one side and bus connections on the opposite side of the S/UNI-VORTEX devices. Bus lines are connected for the simulation purposes with 0.4-inch stubs. The total height of the S/UNI-VORTEX/S/UNI-DUPLEX assembly is about 442 mm (17.4 inches), and the main bus line is about 16.2-inch long (with 0.4-inch spacing between ICs). 4.3.1 Many-to-Single In-line Bus Configuration FIGURE 19 shows the simulation results for the in-line placement in the Receive Data direction. FIGURE 19. In-line Component Placement Simulation VORTEX 10 VORTEX 5 VORTEX 1 DUPLEX In-line; 1 active and 10 tri-stated outputs Controlled impedance bus (~50ohm) 50=-=100 50=-=100 T 1 ATLAS 2 A ATLAS ATLAS input, simulated at two different positions B Unterminated. Vortex-10 to ATLAS-2 C 68 termination Vortex-5 to ATLAS-2 Unterminated. Vortex-10 to ATLAS-1 3.5V 0V -1.0V 0ns 5 nsec/div 50n 0ns 5 nsec/div 50n 0ns 5 nsec/div 50n 3.5V 68 termination Vortex-10 to ATLAS-1 68 termination Vortex-10 to ATLAS-2 68 termination, DUPLEX to ATLAS-2 0V -1.0V 0ns 5 nsec/div 500 mV/div 50n 0ns 5 nsec/div 500 mV/div 50n 0ns 5 nsec/div 50n 27 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION The S/UNI-ATLAS is connected in two configurations marked as 1 at the bus end, and 2 at the center of the bus. A serial resistor is placed at the beginning of the trace connecting to the S/UNI-ATLAS. The LineSim enables one device at a time to transmit towards the S/UNI-ATLAS. The graphs in column A show simulation with the S/UNI-ATLAS connected at the bus end. The higher row shows a signal at the S/UNI-ATLAS without any resistive termination. The lower graphs show the same simulation with a 68 ohm resistor placed at the junction towards the S/UNI-ATLAS. It is clearly visible that the serial termination provides a significant improvement in the signal quality. However, the bus-end configuration (1) creates a very long flat shelf at the rising and falling edges of the signal. The edge distortion on the transmission line, shown in FIGURE 10 (flat shelf), manifests itself here as well. This distortion is inherent to the end-of-bus placement due to the very long-time needed to bounce the signal from the opposite bus end (bounce at the S/UNI-DUPLEX). The graphs in columns B and C show signals with the S/UNI-ATLAS placed at the bus center. The top graph in column B shows the signal without termination, and the lower graph shows the same signal with a 68 ohm serial resistor termination. The graphs in column C show simulation with a 68 ohm serial resistor termination and the S/UNI-VORTEX #5 or the S/UNI-DUPLEX as a driver. FIGURE 20 shows the simulated signal at the S/UNI-ATLAS that is connected at the center as a function of the serial termination resistor. FIGURE 20. S/UNI-VORTEX-10 to S/UNI-ATLAS-2 vs. Serial Resistor 3.5V No termination 33 termination 68 termination 100 termination 0V -1.0V 0ns 5 nsec/div 500 mV/div 50n 0ns 5 nsec/div 50n 0ns 5 nsec/div 50n 0ns 5 nsec/div 50n The serial resistor eliminates non-monotonic shape of the simulated signals. At the same time, the average slope of the rising and falling edges is decreased. To conclude, the resistor value between 68 and 100 ohms is optimal for the in-line Utopia bus configuration. 28 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 4.3.2 Single-to-many In-line Bus Configuration This simulation was conducted with the S/UNI-ATLAS / S/UNI-APEX connected at the bus end and at the bus center. FIGURE 21 shows the simulation results for the unterminated bus. FIGURE 21. Simulation with S/UNI-ATLAS Driving In-line Bus VORTEX 10 VORTEX 5 VORTEX 1 DUPLEX In-line inputs Controlled impedance bus (~50ohm) 1 2 Unterminated bus ATLAS driver, simulated at two different positions ATLAS ATLAS A ATLAS 1 to VORTEX 10 3.5V B ATLAS 1 to VORTEX 5 C ATLAS 1 to DUPLEX ATLAS at the bus end. No termination 0V -1.0V 0ns 5 nsec/div 50n 0ns 5 nsec/div 50n 0ns 5 nsec/div 50n 3.5V ATLAS 2 to VORTEX 10 ATLAS 2 to VORTEX 5 ATLAS 2 to DUPLEX ATLAS at the bus center. No termination 0V -1.0V 0ns 5 nsec/div 500 mV/div 50n 0ns 5 nsec/div 500 mV/div 50n 0ns 5 nsec/div 500 mV/div 50n The signal transmitted from the S/UNI-ATLAS 1 at the bus end has a flat shelf at the S/UNI-VORTEX 10 input and multiple back-reflections on all destinations. The simulated signal transmitted from the S/UNI-ATLAS 2 connected at the bus center shows multiple bumps on all inputs. To clean back-reflections, signal conditioning attempts were made. The signal was simulated with serial 29 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION termination resistors placed near the bus ends. A configuration with a buffer driven bus was also tested. FIGURE 22 shows the simulation results. FIGURE 22. S/UNI-ATLAS to Bus In-line with Termination Resistors VORTEX 10 VORTEX 5 VORTEX 1 DUPLEX In-line inputs Controlled impedance bus (~50ohm) 33 ATLAS or Buffer T 1 33 A A1 3.5V ATLAS B1 B C1 C ATLAS to DUPLEX ATLAS to VORTEX 10 ATLAS to VORTEX 5 0V -1.0V 0ns 5 nsec/div 500 mV/div 50n 0ns 5 nsec/div 500 mV/div 50n 0ns 5 nsec/div 500 mV/div 50n A2 3.5V Fairchild 74LCX2244SC to VORTEX-10 B2 Fairchild 74LCX2244SC to VORTEX-5 C2 Fairchild 74LCX2244SC to DUPLEX 0V -1.0V 0ns 5 nsec/div 500 mV/div 50n Buffer driving bus with 2 x 22 0ns 5 nsec/div 500 mV/div 50n 0ns 5 nsec/div 500 mV/div 50n The upper row, with graphs A1, B1, and C1, shows a signal on the bus driven with the S/UNI-ATLAS. The lower row, with graphs A2, B2, and C2, shows a signal on the bus driven with the Fairchild 74LCX2244SC. The S/UNI-ATLAS driven bus simulates a saw-tooth type of signal due to an energy split at the T joint and an energy loss in serial resistors. In FIGURE 21, it is easily visible, with the upper right graph showing very sharp edges, as the bus energy flows in one direction and reaches its destination point (no splits). 30 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION In FIGURE 22, the 33 ohm termination resistors give an improved signal quality, suppressing most of the non-monotonic ripples at the bus ends. However, the center of the bus still simulates a signal with non-monotonic edges. A workaround is to insert 68 ohm serial resistors at the stubs towards the S/UNI-VORTEX #4/5/6. This workaround eliminates non-monotonic edges, though complicating the layout in which a large number of resistors (five for each bus line) must be used. A serial resistor also decreases edge speed. In search of monotonic edges, a relatively slow 74LCX2244SC 3.3 V line driver (with 5 V compatible inputs) was used as a bus driver. The signal edges, shown on graphs A2, B2, and C2 in FIGURE 22, are monotonic without any overshoots or undershoots. The signal at the S/UNI-VORTEX-5 (bus center) shown in graph B2 simulates slow and monotonic transition across 0.8 V and 2.0 V. In addition, a major timing trap awaits a designer. Slow buffers inherent long propagation delay time, specified in the Fairchild data sheet at tmin = 1.5 ns and tmax=7.5 ns. A higher clock skew is also guaranteed. The propagation delay variation of that magnitude may "kill" bus timing. The faster drivers, such as LPT, LVC, ALVC, or ALVCH, show simulation with very non-monotonic edges. We were unable to simulate the monotonic signal with less than three serial termination resistors for each bus line. The energy split effect at the T-joint and back-reflections cannot be overcome (with S/UNIATLAS I/O pad). FIGURE 23 shows the S/UNI-APEX to the Any-PHY in-line bus simulation. 31 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 23. S/UNI-APEX to Bus In-line with Termination Resistors VORTEX 10 VORTEX 5 VORTEX 1 DUPLEX In-line inputs Controlled impedance bus (~50ohm) 33 T 33 A A 3.5V APEX B B APEX to VORTEX 5 C C APEX to VORTEX-1 APEX to VORTEX 10 2.5 ns 4.5 ns 0V -1.0V 0ns 5 nsec/div 500 mV/div 50n 0ns 5 nsec/div 500 mV/div 50n 0ns 5 nsec/div 500 mV/div 50n A split configuration was simulated in an attempt to find the solution to get monotonic signals. FIGURE 24 shows the bus divided into two branches. 32 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 24. S/UNI-ATLAS Driving Dual-branch Bus VORTEX 10 VORTEX 5 VORTEX 1 DUPLEX In-line inputs Controlled impedance bus (~50ohm) ATLAS driver, 15 15 ATLAS ATLAS to VORTEX 8 ATLAS to VORTEX 5 ATLAS to DUPLEX 3.5V 0V -1.0V 0ns 5 nsec/div 500 mV/div 50n 0ns 5 nsec/div 500 mV/div 50n 0ns 5 nsec/div 500 mV/div 50n The signal is similar to the one shown in the previous 33 ohm in-line simulation in FIGURE 22. Non monotonic edges are simulated on some inputs. The signal is more saw-tooth like with the lower amplitude. In turn, the timing of logic high (above 2.0 V) is adversely affected. The multiple energy split on the T-joints (and energy loss in serial resistors) distorts the square wave into a triangle wave. In technical literature, this bus connection is called a "crow-feet" configuration. The conclusion for the one-to-many and many-to-one in-line configurations are: The best placement of the S/UNI-ATLAS / S/UNI-APEX driving directly the bus is at the center of the bus, with some non-monotonic signal near the bus center An additional high-speed bus driver with dedicated lines at the central position provides a "good" signal, however, resulting in a more complex circuit and the penalty of a significant propagation delay and skew. - 33 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 4.4 Utopia and Any-PHY Dual Bus Offset Configuration FIGURE 25 shows the Utopia/SCI-PHY Receive Direction dual bus with an offset component placement that fits onto the 6U double eurocard, compatible with a standard cPCI shelf. FIGURE 25. Offset Bus Configuration LVDS Interfaces VORTEX, DUPLEX driver Only one of the devices (VORTEX/DUPLEX) driving bus at any time DUPLEX VORTEX 1 VORTEX 2 VORTEX 3 VORTEX 4 VORTEX 5 Termination 50 ATLAS VORTEX 6 41 mm 1.62" Total assembly 226 mm 8.89" Bus trace length 207 mm 8.15" VORTEX 7 91.5 mm 3.6" VORTEX 9 VORTEX 8 APEX 15.2 mm 0.6" VORTEX 10 Input The bus is split into two uni-line sections. The first section connects to five devices and the second one connects to six devices. A short trace with a terminating resistor connects to the S/UNI-ATLAS. The S/UNI-VORTEX/S/UNIDUPLEX BGA package has the Receive Direction Utopia bus interface placed in the upper right corner of the SBGA package (as shown above). It is natural to have the bus running on that side of the device. 34 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 4.4.1 Many-to-single Dual Offset Bus Simulation FIGURE 26 shows the S/UNI-DUPLEX / S/UNI-VORTEX to S/UNI-ATLAS signals simulated with the dual bus offset configuration. FIGURE 26. Receive Data Offset Bus Signal Simulation VORTEX 5 VORTEX 1 VORTEX 10 DUPLEX Offset configuration; 1 active and 10 tristated outputs Controlled impedance bus (~50ohm) 50=-=100 ATLAS input with serial termination resistor A Vortex-10 to ATLAS 3.5V ATLAS B C DUPLEX to ATLAS Vortex-6 to ATLAS No Termination 0V -1.0V 0ns 5 nsec/div 50n 0ns 5 nsec/div 50n 0ns 5 nsec/div 50n 3.5V 2.8 ns 6.0 ns 68 Termination 0V -1.0V 0ns 5 nsec/div 500 mV/div 50n 0ns 5 nsec/div 500 mV/div 50n 0ns 5 nsec/div 500 mV/div 50n The upper row of graphs presents a signal at the S/UNI-ATLAS without any termination resistors. Each curve has a different driver placement on the bus. Multiple back-reflections are clearly visible. The lower row of graphs is for the 68 35 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION ohm serial termination. The simulation shows a monotonic signal and low overshoots/undershoots for all output points. However, all curves are "rounded" with an adverse effect on timing. The most lower-right graph shows hypothetical square wave in comparison to a distorted saw-tooth one. It is clearly visible that timing is shifted by 2.8 to 6.0 ns. FIGURE 27 shows the simulated signal at the S/UNI-ATLAS versus the termination resistor. The driver for the simulation is the S/UNI-DUPLEX. FIGURE 27. S/UNI-DUPLEX to S/UNI-ATLAS vs. Termination Resistor 3.500 volts 0ohm 33ohm 68ohm 100ohm 500 mV/div 0.0 volts -1.000 volts 0.000ns 5 nsec/div 50.000ns 0.000ns 5 nsec/div 50.000ns 0.000ns 5 nsec/div 50.000ns 0.000ns 5 nsec/div 50.000ns The resistor value between 68 and 100 ohm provides an adequate termination for the monotonic edges and low overshoots/undershoots. The higher the resistor value, the slower the rising and falling edges are, due to the low-pass filter effect. Also, branches split the signal edge energy amplifying the saw-tooth (triangle) effect, as seen in the simulation. 4.4.2 Single-to-many Dual Offset Bus Simulation The S/UNI-ATLAS to the S/UNI-DUPLEX / S/UNI-VORTEX with a dual bus offset configuration places the S/UNI-ATLAS at the center of the bus. The first simulation is done with the bus placed in a double uni-line configuration. The interface on the S/UNI-VORTEX SBGA is at the center of the right side of the package, and the bus flows naturally along that side. FIGURE 28 shows the offset configuration and simulated bus signals. 36 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 28. One-to-many in Dual Bus Offset Configuration VORTEX 9 VORTEX 5 VORTEX 1 Offset configuration; 11 inputs VORTEX 10 VORTEX 8 VORTEX 2 DUPLEX Controlled impedance bus (~50ohm) ATLAS driver A VORTEX 9 and 10 3.5V ATLAS B VORTEX 4 and 5 C VORTEX 1 and DUPLEX 0V -1.0V 0ns 5 nsec/div 50n 0ns 5 nsec/div 50n 0ns 5 nsec/div 50n The S/UNI-ATLAS to the S/UNI-DUPLEX / S/UNI-VORTEX simulated signals show multiple back-reflections and non-monotonic edges on all destination points. Each graph shows two waveforms. We were unable to find an easy way to implement a termination solution. A configuration with multiple serial termination resistors, distributed along the bus, simulates saw-tooth (triangle) signals with a variable level of non-monotonic edges. The next exercise is with a redesigned offset bus. 4.5 Utopia and Any-PHY Single Bus Offset Configuration The bus was changed to minimize the total length of copper traces. FIGURE 29 shows the layout and bus dimensions. 37 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 29. Single Bus Offset Component Placement LVDS Interfaces VORTEX/DUPLEX Transmit Data DUPLEX VORTEX 1 VORTEX 2 VORTEX 3 VORTEX 4 Total assembly 238 mm 9.37" Termination 33 41 mm 1.62" ATLAS Bus trace length 207 mm 8.15" VORTEX 5 VORTEX 6 VORTEX 7 VORTEX 8 VORTEX 9 81.3 mm 3.2" APEX 38.1 mm 1.5" Termination 33 Output VORTEX 10 15.2 mm 0.6" 31 mm 1.22" Input The serial termination resistors were placed symmetrically in both branches of the bus line. The signal was simulated with and without termination resistors. FIGURE 30 shows the simulation results. The simulation shows an improvement at most destinations with symmetrically placed termination resistors. The middle of the bus S/UNI-VORTEX 5 input has the least significant improvement and shows the non-monotonic edges. The only solution is to insert a serial termination resistor (33 ohm) next to the input. However, the area around the S/UNI-VORTEX 5 is congested with bus lines, and it may be challenging to place multiple termination resistors at that place. 38 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION An unexpected minor signal degradation appears at the S/UNI-VORTEX 2 and 8 with the termination resistor, a small bump on the edges at about 1.5 V is visible in the lower row (2A and 2C). The middle of the bus (2B) shows a decrease in ripples. FIGURE 30. S/UNI-ATLAS in a Single Bus Offset Configuration VORTEX 9 VORTEX 5 VORTEX 1 Offset configuration; 11 inputs VX 8 VORTEX 10 1 2 2 VX 2 DUPLEX 1 Controlled impedance bus (~50ohm) 33 33 APEX driver ATLAS A 3.5V B C No Termination 500 mV/div 0.0 V -1.0V 1A 0ns 5 nsec/div 50ns 0ns 1B 5 nsec/div 50ns 0ns 1C 5 nsec/div 50ns 33 at position 1 2A 0ns 5 nsec/div 50ns 0ns 2B 5 nsec/div 50ns 0ns 2C 5 nsec/div 50ns The serial termination resistors in both branches can be placed at position 1 or 2, as shown in FIGURE 30 above. Position 1 is preferable, and position 2 may deliver the signal with slightly higher non-monotonic edges. The symmetry in each bus line has to be maintained. The S/UNI-VORTEX-5 still has the nonmonotonic edge. 39 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 4.6 Multi-Branch Offset Configuration The industry nickname for layout with a longer trace branching at a single point is "crow-feet". This exercise is completed with connections similar to crow-feet, though not exactly the same. The bus is split into two chunks with five and six devices attached. Each set is fed with a five-inch long line and a 10 ohm serial resistor. FIGURE 31 shows the simulation results. FIGURE 31. S/UNI-ATLAS in Crow-feet Configuration VORTEX 9 VORTEX 5 VORTEX 1 Offset configuration; 11 inputs VORTEX 10 10 5" 10 DUPLEX Controlled impedance bus (~50ohm) 5" ATLAS driver A 3.5V ATLAS B C No Termination 0.0 V -1.0V 0ns 5 nsec/div 500 mV/div 50ns 0ns 5 nsec/div 50ns 0ns 5 nsec/div 50ns 2x10 0ns 5 nsec/div 50ns 0ns 5 nsec/div 50ns 0ns 5 nsec/div 50ns Simulated signals without terminations have less significant bumps than the configuration shown in FIGURE 30. Termination resistors can be increased up to 33 ohm, decreasing the back-reflections and applying a penalty of more sawtooth like curves. The energy split at the S/UNI-ATLAS output and the dumping effect introduced by inserted resistors decrease the edge speed. Also, inputs near the trunk connection still exhibit significant ringing. 40 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 4.7 S/UNI-APEX to Any-PHY Bus FIGURE 32 shows the S/UNI-APEX driving offset configuration bus. FIGURE 32. S/UNI-APEX to Bus Simulation VORTEX 9 VORTEX 5 VORTEX 1 Offset configuration; 10 inputs VORTEX 10 DUPLEX Controlled impedance bus (~50ohm) 33 33 APEX driver APEX A 3.5V B C No Termination 500 mV/div 0.0 V -1.0V 0ns 5 nsec/div 50ns 0ns 5 nsec/div 50ns 0ns 5 nsec/div 50ns 2x33 0ns 5 nsec/div 50ns 0ns 5 nsec/div 50ns 0ns 5 nsec/div 50ns The unterminated simulated waveforms (upper row of graphs) show significant back-reflections and rounded edges. The signal has a visibly better logic high/low plateau than the one shown in FIGURE 30 that has the same configuration with the S/UNI-ATLAS driver. This can be attributed mainly to the higher driving current on the pc3b04 I/O pad. The minor improvement is a smaller number of inputs attached to the Any-PHY bus (the S/UNI-DUPLEX is not connected). Back-reflections are also smaller due to a lower edge speed (see edges and driving current in FIGURE 17). One of the graphs above shows two curves to visualize signal distortion when an idealized square wave is compared to the simulated wave at the destination point. 41 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION A comparison of FIGURE 30 and FIGURE 32 shows that current drive capability is critical to deliver a better signal. Edge speed may have an adverse effect, with faster edges creating higher back-reflections and needing better termination. FIGURE 33 shows the S/UNI-APEX driving bus in a near-crow-feet configuration. FIGURE 33. S/UNI-APEX to Any-PHY bus in Crow-feet Configuration VORTEX 9 VORTEX 5 VORTEX 1 Offset configuration; 11 inputs VORTEX 10 10 5" 10 DUPLEX Controlled impedance bus (~50ohm) 5" APEX driver A 3.5V APEX B C No Termination 0.0 V -1.0V 0ns 5 nsec/div 50ns 0ns 5 nsec/div 50ns 0ns 5 nsec/div 50ns 2x10 0ns 5 nsec/div 50ns 0ns 5 nsec/div 50ns 0ns 5 nsec/div 50ns 2x33 0ns 5 nsec/div 50ns 0ns 5 nsec/div 500 mV/div 50ns 0ns 5 nsec/div 50ns Two five-inch long lines connect to a set of five devices each. Serial resistors dump back-reflections and, at the same time, increase the saw-tooth effect. 42 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION A comparison of the graphs from FIGURE 31 and FIGURE 33 shows that the higher current driver (S/UNI-APEX) with a lower edge speed simulates the signal with less bumps in a similar configuration (the more driving capability, the better the wave shape). The penalty for a high speed and high current I/O pads is increased parallel switching ground cross talk, which may add up to a significant voltage and corrupt data, and can be a serious problem in the high-speed silicon. To maintain signal integrity with lower current I/Os, the solution is to reduce the number of integrated circuits on the bus, or reduce the physical dimensions of the bus (maybe double-sided component placement). Decreasing bus clock speed may ease timing problem, however, backreflections on fast edges will still exist. Possible solutions: Monotonic edges may be achieved with multiple serial termination resistors distributed across the bus line. That requires a large number of resistors across multiple buses adding easily to hundreds of additional resistors assembled on a board. Buried resistors may help elevate real estate and assembly issues. Buried resistors may increase substantially board price. If progress in PCB technology allows for cost effective solutions, then designer should investigate that technology. However, a decision to implement new technology should be carefully simulated and evaluated before board is laid out and manufactured. 4.8 Clock Distribution Simulation 4.8.1 Clock Transmission Line The clock lines need special attention to provide absolutely monotonic transition between 0.8 V to 2.0 V, and a reasonable margin below and above the logic thresholds without major overshoots/undershoots. To prevent forcing current into the silicon, the overshoot has to be kept within clamping voltage levels. The clock signal transmission analysis, presented in one of the previous sections, shows that bus-type clock distribution creates an unacceptable shelf on the clock edge. Therefore, we evaluated semi-dedicated clock lines to eliminate shelf distortion. Devices are grouped two or three each, with four or six inputs connected together. The symmetry at the line end is maintained. A single transmission line drives each group. The total number of five clock lines (and five buffers) is required in this configuration. FIGURE 34 shows the simulated clock distribution circuit for the in-line configuration. The S/UNI-VORTEX / S/UNI-DUPLEX requires two 52 MHz RCLK and TCLK clock signals. Multiple inputs can share the same clock line. 43 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 34. Clock Distribution Simulation VORTEX 10 VORTEX 5 VORTEX 1 DUPLEX 1.5" Clock inputs grouped by four or six 16" 8.6" Buffer 52MHz APEX ATLAS Clock to B Clock to C IDT74LVCH16244.... 3.3V 150 Controlled impedance lines with Thevenin terminations A B 110 C Clock to A 7.0V This row Unterminated 0V -2.0V 0ns 5 nsec/div 1 V/div 50n 0ns 5 nsec/div 1 V/div 50n 0ns 5 nsec/div 1 V/div 50n 3.5V This row with Thevenin termination 110//150ohm 0V -1.0V 0ns 2 nsec/div 500 mV/div 1.6n 20n 0ns 2 nsec/div 500 mV/div 0.96n 20n 0ns 2 nsec/div 500 mV/div 1n 20n The clock is placed arbitrarily on one side of the bus. The clock is buffered with an IDT74LVCH16244 line driver. This placement may require a clock skew adjustment for each line. Each line is terminated next to the T-joint with the Thevenin termination. The simulation shows a clock signal at three different destinations (see FIGURE 34). The upper row shows an unterminated signal with the LineSim "oscilloscope" set at 1 V/div and 5 ns/div. The lower row shows terminated clocks with the zoom at 0.5 V/div and 2 ns/div for a better view on the clock edges. The simulated clock on all destinations is monotonic with a moderate overshoot/undershoot, with some margin on logic high or low. Visible waves on the clock edges in column A are most likely from the highest number of 44 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION capacitive loads driven (six inputs). The solution is to decrease the number of inputs driven by the specific buffer. The logic high overshoots to about 3.4 V, and logic, and the logic low extends to about -0.7 V. The low overshoot may generate some current through clamping diodes. The positive edge transition across 0.8 V to 2.0 V is in a range 0.96 ns to 1.6 ns at different destination points. Clock inputs can be split further into smaller sections to improve edge speed and decrease skew. FIGURE 34 shows 150 ohm to Vcc and 110 ohm to ground. The equivalent impedance is about 63 ohm. Signals with other combinations of resistor values are shown in FIGURE 35. CLOCK1 was simulated at the "A" destination as a function of a resistor value in the Thevenin termination. FIGURE 35 shows the simulated curves. FIGURE 35. Clock signal at A vs. Thevenin Termination A 3.5V 100/100ohm at A B 3.5V 150/110ohm - Vcc/GND at A C 110/150ohm - Vcc/GND at A 2.0 0.8 0V 0.0 -1.0V 0ns 5 nsec/div 500 mV/div 50ns -1.0V 0ns 5 nsec/div 500 mV/div 50ns 0ns 5 nsec/div 50ns The duty cycle of the clock is set to 55%. Graphs show little change in the signal shape with a different termination. The most visible is the amplitude variation. Graph B shows a logic "low" level that extends to -0.7 V, and this level may force the current through the clamping diodes. Resistor values in Graphs A and C provide better termination. A buffer inserted in the clock/data path introduces propagation delay and edge skew. Slower buffers and "general purpose" data buffers may not be suitable if bus timing becomes critical. 4.8.2 Buffer Evaluation While working on the clock line simulation, a number of buffers was tested. A significant difference in signal performance was observed. FIGURE 36 shows the 45 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION clock signal versus different line drivers at the "A" destination with an unterminated transmission line (shown in FIGURE 34). FIGURE 36. Clock vs. Line Driver Type on Unterminated Line Generic 74LVxxx-Line_Driver 3.5V Fairchild 74LCX244MCT 3.500 volts 3.5V IDT IDT74LVCH16244 This one was used for the clock line simulation. 500 mV/div 500 mV/div 500 mV/div 0.0 volts 0.0 volts 0.0 volts -1.0V 0ns 2 nsec/div 20ns -1.000 volts 0.000ns 2 nsec/div 20.000ns -1.0V 0ns 2 nsec/div 20ns TI SN774ALVCH16244 3.500 volts 3.5V IDT IDT74ALVCH16244 3.5V PERICOM PI74ALVCH16244V 500 mV/div 500 mV/div 500 mV/div 0.0 volts 0.0 volts 0.0 volts -1.000 volts 0.000ns -1.0V 2 nsec/div 20.000ns 0ns 2 nsec/div 20 ns -1.0V 0ns 2 nsec/div 20ns IDT, 100MHz 1-to-10 Clock Driver IDT74FCT3807/A 3.5V 3.500 volts PHILIPS 74ALVT16244 7.000 volts PHILIPS 74ALVT16244 500 mV/div 500 mV/div 1 V/div 0.0V -1.0V 0.000ns 0.0 volts 0.0 volts 2 nsec/div 20ns -1.000 volts 0.000ns 2 nsec/div 20.000ns -2.000 volts 0.000ns 5 nsec/div 50.000ns The same type of the ALVCH16244 driver, from three major manufacturers, is shown in the second row. The simulation shows a difference in waveforms, which may question the reliability of the IBIS models or compliance with industry standards for the same type of a silicon device. Discrepancies point to a need for performance verification in critical applications, where a new and unknown part is about to be implemented. The fastest rising edge is simulated with the 74ALVT16244 made by Philips Semiconductor. The signal is shown with two time-bases and gains for better view. The driver is simulated for the clock signal distribution and performed with significantly higher overshoots than the IDT driver shown in FIGURE 35. 46 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION The unterminated signals show monotonic clock edges for most buffers. Signal peaks extend beyond clamping diode ranges on Vcc and ground rails, and a proper termination is needed for most drivers. NOTE: Both clock edges - rising and falling - must be monotonic without any flat shelves and bumps in the transition region of 0.8 V to 2.0 V. 4.8.3 Clamping Diodes Current It was mentioned previously, that an overshoot on digital inputs may cause an interference to adjacent I/O pads. This section tries to address the problem by the current simulation at clock input. FIGURE 37 shows the simulation setup and simulation results. FIGURE 37. Clock Line Current Driver C_pin 1 2 16" 3 4 L_pin R_pin C_comp Driver 16" Driver 16" 0.1 A 10V 7.72V 4.28V B No clamping diodes 10V Driver = IDT74ALVC16244 Clamping diode effect C Signal at special pad 5V 0V 0.0V 1 V/div 0V -1.14V -5.31V -8.0V 0ns 10 nsec/div 2 V/div 100ns -8.0V 0ns -4V 10 nsec/div 2 V/div 100ns 0ns 5 nsec/div 50ns The setup and procedure to visualize and determine the clamping diode current is as follows: The first setup (A). Four I/O pads, at the end of a 16-inch long transmission line, are substituted with RLC elements equivalent to the IBIS model C_comp, C_pin, L_pin, and R_pin. Clamping diodes are eliminated. The IDT74ALVC16244 buffer drives the transmission line. Graph A shows the simulated circuit behaving as a resonance circuit with signal peaks at -5.31 V and +7.72 V, resulting in a 13.03 Vp-p. 47 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION The second setup (B). The S/UNI-VORTEX/S/UNI-DUPLEX devices are placed at the line end. Graph B shows the clock signal suppressed by the clamping diodes. The voltage peaks are at -1.14 V and 4.28 V. The both clamping diodes to Vcc and to ground conduct current. FIGURE 38. Clock Line Current Driver C_pin 1 2 16" 3 4 L_pin R_pin C_comp Driver 16" Driver 16" A 10V 7.72V 4.28V B No clamping diodes 10V Driver = IDT74ALVC16244 Clamping diode effect C Signal at special pad 5V 0.1 0V 0.0V 1 V/div 0V -1.14V -5.31V -8.0V 0ns 10 nsec/div 2 V/div 100ns -8.0V 0ns -4V 10 nsec/div 2 V/div 100ns 0ns 7.5 mV 5 nsec/div 50ns D 2.0 mV Voltage across 0.1ohm shunt 0V -2.4 mV 2 mV/div -9.6 mV 0ns 5 nsec/div 50ns The third setup (C). A special I/O pad in the IBIS model was created with minimum values of the parasitic RLC element. The pad is placed as shown at position C in the above figure. A 0.1 ohm current-sensing resistor is placed at the I/O input. The external RLC elements, matching the IBIS model, are inserted before the sensing resistor. As a result, the current flowing through the C_comp and C_pin is not included at the 0.1 ohm serial resistor. Only the clamping diode current creates a voltage drop across the current-sensing resistor. The simulated current reaches a negative peak at about -96mA and a positive peak at about +75 mA. However, the peaks coincide with signal edges. It is not clear, at this time, if this is attributed to the clamping diode currents. The flat pedestals on graph D converts to about 20 mA and -24 mA. Those levels are 48 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION most likely due to clamping diode currents. The highest peaks of the simulated current should not trigger the latch-up condition. The clamping current may cause interference into another data/address lines. The PMC-Sierra 3.3 V 0.35 u devices are tested for I/O pad latch-up, up to 200 mA. Properly designed I/O pads help to minimize the digital crosstalk through the silicon. The above exercise highlights a need for a proper termination, especially on clock lines with dedicated drivers on each line. The data/address lines, in a bustype configuration may show significant overshoot peaks due to accumulated capacitive loads and long unterminated traces. 4.8.4 Crosstalk and EMI The crosstalk and EMI (electromagnetic interference) for the data and clock transmission lines are not simulated in this document. Clock lines tend to create very strong harmonics in the electromagnetic field that may be subject to FCC regulations. The edges of the clock lines are faster than the data lines, which may cause interference to the data lines. Therefore, special care is needed for the clock transmission line layout and termination. 49 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 5 DATA SHEET DERIVED TIMING The following sections present the results for signal integrity and timing simulation using the LineSim (HyperLynx) and Timer Designer (Chronology) software tools. The goal of these exercises is proper calculation of timing margins with unconventional use of IBIS models, simulation tools, and datasheet AC timing. 5.1 VORTEX Chipset Hold and Setup Time The setup and hold time derived from corresponding datasheets for the VORTEX chipset is shown in FIGURE 39 and FIGURE 40 below. The smallest margin on hold time equal to 0 ns (zero nanosecond), as shown in section A of FIGURE 40, is at the interface with the S/UNI-ATLAS polling S/UNI-VORTEX and S/UNIDUPLEX. If signal integrity is not included in the timing calculations, bus timing, derived directly from a data sheet, may lead to false conclusions. Timing margins, based on signal integrity, are described in the following sections. FIGURE 39. VORTEX Chipset Data Sheet Timing 0ns 10ns 20ns 50 MHz 8.0 1.75 APEX W AN TX Propagation Delay with 40 pF APEX APEX APEX 1.75 APEX 3 ATLAS SETUP/HOLD 0.75 ns Hold M i 1 50 MHz ATLAS Propagation Delay with 50 pF ATLAS 1.0 12.0 APEX W AN RX SETUP/HOLD 2.0 ATLAS ATLAS 0.65 ns Hold Margin 0.35 1.0 ns Hold Margin 3.5 APEX W AN TX SETUP/HOLD 0 50 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 40. VORTEX Chipset Data Sheet Timing 0ns 10ns 20ns A 50 MHz 12 1 ATLAS Propagation Delay with 50 pF load ATLAS ATLAS 1 ATLAS 3 APEX Any/PHY Loop RX SETUP/HOLD 0.75 ns Hold Margin 0.25 3 VORTEX SETUP/HOLD 3 DUPLEX SETUP/HOLD 0.0 ns Hold Margin 1 0.0 ns Hold Margin 1 B 50 MHz 10 1.75 APEX Loop Any/PHY TX Propagation Delay with 80 pF load APEX APEX APEX 3 ATLAS SETUP/HOLD1 0.75 ns Hold Margin 1 3 VORTEX SETUP/HOLD1 1 3 DUPLEX SETUP/HOLD1 1 C 50 MHz 12 2 VORTEX/DUPLEX Propagation Delay with 50 pF load VORTEX/DUPLEX VORTEX/DUPLEX VORTEX/DUPLEX 2.0 ns Hold Margin 4.0 APEX Any/PHY Loop TX SETUP/HOLD 0.0 3 ATLAS SETUP/HOLD2 1 4.0 1.0 ns Hold Margin 51 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 5.2 S/UNI-APEX I/O Drivers The S/UNI-APEX interfaces are specified in the data sheets as follows: - Any-PHY TX Loop - Any-PHY RX Loop - UTOPIA WAN side - UTOPIA WAN side - SSRAM - SDRAM 80 pF load 50 pF load 40 pF load 40 pF load 40 pF load 20 pF load 52 MHz 52 MHz 52 MHz 52 MHz 80 MHz 80 MHz pc3b04/pc3t04 pc3b04/pc3t04 pc3b04/pc3t04 pc3b01 pc3b04/pc3t04 pc3t02 The in-line example placement with clock lines is shown in FIGURE 47. An increase in RAM size may deem this placement obsolete. The drawing is done in 1:1 scale and helps to visualize the size of the S/UNI-APEX assembly. To clarify the simulation process flow, FIGURE 41 shows the S/UNI-APEX I/O pc3b04 pad driving capability (also shown in FIGURE 17). FIGURE 41. S/UNI-APEX IBIS-typical with 50 ohm Load APEX-testchip, pc3b04 loaded with 50 ohm, model strong-typical-weak 3.5V pc3b04, strong pc3b04, typical pc3b04, weak IBIS model pc3b04 50ohm GND 0V -1.0V 0 500 psec/div 500 mV/div dV = 1.21 V, dt = 2.5 ns 5ns This simulation was completed with the IBIS model set at "strong-fast", "typical", and "weak-slow". This pad drives the SSRAM Address (also the Utopia L2 and Any-PHY buses). The "strong" IBIS model is created with an I/O performance at -40 C and 3.63 V. The "typical" model is at 25 C and 3.3 V. The "weak" model is at +80 C and 2.97 V. 52 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION As expected, the "strong" IBIS model delivers the highest current and the fastest edge. The "weak" model is significantly slower. Variation in edge speed may create timing problems within the operating temperature range. The S/UNI-APEX data sheet specify timing at 50 % of output swing, what is equivalent to 50 % of the power rail (+3.3 V / 2 = 1.65 V). FIGURE 42 shows the IBIS model pc3b04 loaded with 40 pF. FIGURE 42. S/UNI-APEX pc3b04 loaded with 40 pF A S/UNI-APEX, pc3t04, slowweak & fast-strong, 40 pF load 3.5 V B 3.5 V S/UNI-APEX, pc3t04, slowweak & fast-strong, 40 pF load This curve shown in Figure. 43. 50 % 500 mV/div 0.95 ns 1.27 ns 2.17 ns 4.0 ns 50 % 500 mV/div 0.70 ns 3.3 ns 1.95 ns 2.28 ns 0.0 -1.0 V 0 ns 1.13 ns 500 ps/div 3.52 ns 0.0 5 ns -1.0 V 0 ns 500 psec/div 5 ns Cursor 1, Voltage = 1.66 V, Time = 3.52 ns Cursor 2, Voltage = 1.67 V, Time = 1.13 ns Delta Voltage = 17.24 mV, Delta Time = 2.39 ns Cursor 1, Voltage = 1.66 V, Time = 3.52 ns Cursor 2, Voltage = 1.67 V, Time = 1.13 ns Delta Voltage = 17.24 mV, Delta Time = 2.39 ns The graph shows the rising and falling edges of the IBIS model slow-weak and fast-strong loaded with 40 pF. Simulation was completed with the capacitor connected to the output without any transmission line and termination resistor. The rising slow-weak edge reaches 50 % at 3.52 ns. The strong-fast edge reaches 50 % at 1.13 ns. Graph B shows timing for TTL logic levels. FIGURE 43. S/UNI-APEX I/O pc3b04, fast-strong with 40 pF and no load A S/UNI-APEX, pc3t04, fast-strong, 40 pF and no load 3.5 V B S/UNI-APEX, pc3t04, fast-strong, 40 pF and no load 3.5 V 0.50 ns 0.26 ns 0.95 ns 1.27 ns 500 mV/div 500 mV/div 0.24 ns 0.80 ns 1.95 ns 0.0 volts 0.0 volts 0.45 ns -1.0 V 0 ns 0.32 ns 1.13 ns 500 p/div 5 ns -1.0 V 0 ns 500 p/div 5 ns Delta Time = 0.81 ps The 50% crossing points for no load and 40 pF loads are at 0.32 ns and 1.13 ns respectively. The TTL levels timing is shown in graph B. 53 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 5.3 S/UNI-APEX- pc3b04/pc3t04 Valid Signal Correction The data sheet derived "Propagation Delay" and "Setup/hold" time needs correction before it can be used for timing simulation based on the bus signal integrity simulation. The following sections try to interpret data sheet AC timing with signal integrity simulation, and to pass collected data to the timing analysis.. The goal of the following exercise is to separate digital circuit delay from I/O pad delay. This is the author's way of interpreting the data sheet, and designers are encouraged to investigate other ways of interpreting data sheets 5.3.1 S/UNI-APEX with 40 pF Load The S/UNI-APEX propagation delay TPSCLK for SSRAM interface is specified in the data sheet at 1.5 ns to 8.25 ns, with 40 pF load at the I/O pad, and measured at 50% of the transition. The propagation delay consists of two factors: digital circuit delay and loaded I/O delay. FIGURE 44 shows a graphical representation of those factors at 80 MHz. FIGURE 44. Propagation Delay for pc3b04 IBIS weak/slow with 40 pF 4.73ns 8.25ns T = 3.52 ns 13.68ns 0ns 80MHz CLOCK Datasheet Propagation Delay at APEX 1.5 A 3.5V 10ns 12.5 8.73 14.0 B 3.5V 6.25 8.25 pc3b04, IBIS fast-strong, no load 2.0V 2.0V 50 % 50 % 0.8V pc3b04, IBIS- slow/weak, 40pF load 0 -1.0V 0 500 psec/div 500 mV/div 5ns 0 -1.0V 3.52ns 4.0 ns 0.27 ns 0.32 ns 13.95 5ns Corrected Valid Data Propagation Delay at APEX 1.45 8.73 The LineSim graph A is positioned in such a way that the pc3b04 weak-slow IBIS model loaded with 40 pF (shown earlier in FIGURE 42) crosses the 50% level at the 8.25 ns mark at the clock scale. The logic high valid signal is reached when the curve crosses 2.0 V at the 8.73 ns mark. A similar procedure applies to the non-valid signal determined around 14 ns on graph B with a fast-strong model and no capacitive load. The 50% line is crossed at 0.32 ns from the IBIS model 54 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION start point. The 50% crossing is aligned with the 14 ns mark derived from the data sheet (12.5 ns + 1.5 ns = 14.0 ns). The signal is invalid after 0.27 ns, when the IBIS model slow-weak without load crosses the logic low at 0.8 V. The lower timing bar shows a corrected TTL-level valid data propagation delay, set at 1.45 ns and 8.73 ns. The TTL-levels are 0.8 V and 2.0 V. The difference is about 14.0 - 13.95 = 0.05 ns for an invalid signal and 8.73 - 8.25 = 0.48 ns for a valid signal. Those few hundreds of picoseconds may not be critical in one design and may become a major issue in another circuit. The 4.73 ns and 13.95 ns points are important for the timing simulation based on the LineSim simulation. The simulation program starts I/O simulation process at those marks (4.73 ns / 12.87 ns). This also means, that the digital delay must not exceed 4.73 ns. The S/UNI-APEX meets the digital delay requirement to be less than 4.73 ns. The difference of 3.52 ns is needed by the slow-weak I/O pad loaded with 40 pF to reach 50 % mark. The I/O also needs 4.0 ns to reach a valid logic level high. The 4.73 ns mark is "time-zero" when an idealized digital signal drives the I/O pad high (or low). The 4.73 ns and 13.68 ns marks are artificially created start points for the LineSim edge that travels along the bus line. Those two points and time differences are entered into timing diagrams (shown later in this document). FIGURE 45 shows the fast-strong IBIS model loaded with 40 pF that is simulated and aligned with the timing bar. FIGURE 45. Propagation Delay for pc3b04 IBIS fast-strong with 40 pF 0ns 80MHz CLOCK 0 Propagation Delay at APEX 1.5 3.5V 4.73ns 8.0ns 6.25 5.22 T=3.67ns 10ns 12.5 13.68ns 8.25 B 3.5V 14.0 2.0V pc3b04, IBIS strong-fast, no load 0.8V 0 0.8V 0 -1.0V 0 0.49 ns 500 p/div 500 mV/div 3.52ns 5ns -1.0V 0.27 ns 0.32 ns 5ns The timing point 4.73 ns, determined with the previous diagram, is also the start point for the pc3b04 strong-fast IBIS model loaded with 40 pF, even if the strong55 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION fast charges 40 pF faster. Our understanding is that the 4.73 ns point is the absolutely worst case digital delay (the longest delay) on the S/UNI-APEX device, and no signal edge can start later than that point. The unloaded strongfast simulation is positioned the same way as on the previous graph. The 13.68 ns point is the start point for both fast-strong and slow-weak IBIS models. The 5.22 ns point (shown above) is the valid ADDRESS with unloaded outputs for the IBIS fast-strong model. This point has no importance to timing simulation; however, it visualizes a relatively long valid signal (from 5.22 ns to 13.68 ns) with the fast-strong model. The pc3b04 IBIS fast-strong and slow-weak models have the artificial start points at 4.73 ns and 13.68 ns, which will be used for the timing diagram. 56 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 6 S/UNI-APEX RAM INTERFACE SIMULATION The S/UNI-APEX interface to SSRAM and SDRAM are simulated and the results are described in the following sections. 6.1 Example of Component Placement FIGURE 46 shows an example of component placement on a standard cPCI card. FIGURE 46. DSLAM Chipset Placement LVDS Interface with FireWire connectors VORTEX/ DUPLEX/ TETRA Optional Sub-board for RAMs DUPLEX RAMs ATLAS VORTEX 1 VORTEX 2 RAMs RAMs Total assembly 228 mm 8.98" APEX RAMs uP VORTEX 9 VORTEX 10 cPCI Bridge 145 mm 5.71" 47.2 mm 1.86" After all the S/UNI-VORTEX and S/UNI-DUPLEX devices are placed, a narrow strip of about 1.89" is left for the S/UNI-APEX, S/UNI-ATLAS and RAM. A high count of components on a board makes it difficult to place all the RAM required for the S/UNI-ATLAS and S/UNI-APEX. The LateWrite or ZBT SRAM and SDRAM associated with the S/UNI-APEX operate at 80 MHz and require special 57 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION attention. The 80 MHz RAM should be placed near the S/UNI-APEX. The 50 MHz S/UNI-ATLAS associated with the RAM may have longer traces or be placed on a daughter board with proper serial termination. 6.2 S/UNI-APEX RAM Bus Configuration Examples FIGURE 47 shows three examples of RAM placement. The Reference Design Core Card has RAMs placed as shown on circuit "3". FIGURE 47. Example of S/UNI-APEX Interface to SSRAM and SDRAM SSRAM 4 ZBT SSRAM LW SSRAM 119 PBGA 1 2 RAM 3 RAM 4 SSRAM 3 Bus trace length 95.2 mm 3.25" SSRAM 2 Total assembly 152 mm 5.98" CLOCK BUFFER RAM 1 RAM 2 14 mm 0.55" 5.04 mm 0.2" SSRAM 512 kb x 18 Address Bus APEX CLOCK SSRAM 1 RAM 1 Clock Address Data 35 mm 1.38" APEX Address Bus APEX CLK Address 58 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE SDRAM 1 SDRAM 2 SDRAM 1 Data SDRAM 2 RAM 2 3 SDRAM 1 SDRAM 2 RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 6.3 Clock Signal to S/UNI-APEX and RAMs Simulation The target for the clock signal integrity simulation is to have monotonic edges and no overshoot exceeding clamping diode ranges, that means for +3.3 V supply rail 3.3 V + 0.6 V = 3.9 V and -0.6 V for logic low. The rising/falling edge slope, dV/dt, must be high, between 0.8 V and 2.0 V. FIGURE 48 shows the results from the clock signal integrity that was simulated at 80 MHz. FIGURE 48. Clock Simulation at 80 MHz SSRAM 119 PBGA RAM 4 (GS88236) RAM 3 15 RAM 2 Buffer CLOCK0 Clock 80MHz -1.0V Clock to SSRAM with 15 ohm at buffer PI74ALVCH16244A 3.5V 44.5mm 1.75" 0.32ns 500 mV/div 0 14 mm 0.55" 0 2 nsec/div Delta Time = 518.519 ps 20ns RAM 1 15 3.500 volts 15 70mm 2.75" 0.49ns Clock 500 mV/div APEX 0.0 volts -1.000 volts 0.000ns 2 nsec/div Delta Time = 370.370 ps 20.000ns Clock to SDRAM with 15 ohm termination 3.500 volts SDRAM 1 SDRAM 2 500 mV/div 0.0 volts -1.000 volts 0.000ns 2 nsec/div Delta Time = 667 ps 20.000ns The clock distributed with the buffer shows monotonic edges with a low overshoot. Clock traces to SSRAM interface have a travel time of 0.32 ns. The buffer is PERICOM PI74ALVCH16244A. 59 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 6.4 S/UNI-APEX - SSRAM Interface 6.4.1 4x1MB SSRAM In-line Configuration at 80 MHz The address bus was simulated with a preliminary IBIS model for ZBT SSRAM GS880Z36 from GSI Technology in pipeline mode. The RAM is 256kb x 36 SSRAM (119 PBGA) requiring 4 MB of RAM in four packages. Clock was set at 80 MHz. FIGURE 49 shows the simulation results. FIGURE 49. Address Bus Simulation for 16MB SSRAM at 80 MHz A APEX-testchip, pc3b04, address, B APEX-testchip, address, pc3b04 weak, no termination strong, no termination 3.5V 3.5V 22 mm 0.87" 500 mV/div RAM 4 SSRAM 119 PBGA 0 0 0 5 nsec/div 500 mV/div 50.000ns -1.0V 0 5 nsec/div 50ns RAM 3 83 mm 3.25" 19 mm 0.75" RAM 1 47 RAM 2 C 3.5 V APEX-testchip, pc3b04, strong, no termination D APEX-testchip, address, pc3b04 weak, no termination 3.5V 500 mV/div 500 mV/div 0 0 -1.0 V 0 2 nsec/div 20 ns -1.0V 0ns 2 nsec/div 20ns Address Bus E APEX-testchip, address, pc3b04 strong, 47ohm after 2nd RAM 3.5V APEX F APEX-testchip, address, pc3b04 weak, 47ohm 3.5V 500 mV/div 500 mV/div 0 0 -1.0V 0 2 nsec/div 20 ns -1.0V 0 2 nsec/div 20 ns The unterminated strong/fast signals, shown on graphs A and C, have visible bumps on both edges and significant overshoot peaks. The unterminated slow/weak on graphs B and D has very monotonic edges with a minor overshoot. The in-line configuration simulates acceptable ADDRESS signal, as shown on graphs E and F, with the 47 ohm serial resistor after RAM-2. 60 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION The DATA from SSRAM to the S/UNI-APEX, in configuration exercised above, with the IBIS model set at strong/fast creates high back-reflections. We were unable to provide a single resistor termination to produce monotonic edges. The DATA bus is bi-directional, adding more difficulties to bus termination. This configuration failed the SSRAM DATA strong/fast simulation. 6.4.2 4x1MB SSRAM Parallel Configuration at 80 MHz FIGURE 50 shows the placement of SSRAMs in 2 x 2 configuration. This component placement requires each RAM chip size at 512 kb x 18 (GS882Z18). The IBIS model available at the present time is for GS880Z18. FIGURE 50. ADDRESS to SSRAM SSRAM, GS882Z18, 119 PBGA RAM 3 RAM 4 APEX, pc3b04, address to four SSRAMS, 2x33 ohm at V split 3.5 V RAM 1 RAM 2 33 500 mV/div Address Bus 0.0 volts APEX -1.0 V 0 ns 1.48 ns 5.52 ns 2 ns/div 20 ns The ADDRESS to SSRAM is simulated with a moderate edge overshoot and almost monotonic edges even without any termination resistor. Graph shown above is for two 33 ohm serial termination resistors. Minor bumps are visible on falling edges near logic low - it should be acceptable for most applications. The DSLAM Core Card Reference Design [4], built with RAM1 and RAM2 only, uses a single serial resistor to reduce back-reflections. Address trace is laid out with T junction. FIGURE 51 shows the DATA bus from S/UNI-APEX to SSRAM. 61 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 51. DATA from S/UNI-APEX to SSRAM DATA from APEX to SSRAM, slow-fast SSRAM, GS882Z18, 119 PBGA 3.500 volts RAM 3 RAM 4 500 mV/div 0.0 volts RAM 1 RAM 2 -1.000 volts 0.000ns 2 nsec/div 20.000ns DATA Bus 22 3.500 volts DATA from APEX to SSRAM, slow-fast, 22 ohm APEX 500 mV/div 0.0 volts -1.000 volts 0.000ns 2 nsec/div 20.000ns The DATA from the S/UNI-APEX to SSRAM needs a serial resistor to prevent signal overshooting with the IBIS fast-strong model. The serial resistor 22 ohm provides some termination. The higher value may be needed to eliminate waves at high and low. The DATA from the SSRAM to the S/UNI-APEX must have a 22 ohm resistor inserted, as shown in the simulation in FIGURE 51. FIGURE 52 shows the simulated DATA signal on the bus from the SSRAM to the S/UNI-APEX. FIGURE 52. DATA from SSRAM to S/UNI-APEX SSRAM, GS84018, 119 PBGA RAM 3 RAM 4 DATA from SSRAM-1 to APEX, slow-fast, 22 ohm 3.5 V 3.500 volts DATA from SSRAM-3 to APEX, slow-fast, 22 ohm RAM 1 RAM 2 500 mV/div 500 mV/div DATA Bus 22 0.0 volts 0.0 volts APEX -1.0 V 0 2 nsec/div 20.000 ns -1.000 volts 0.000ns 2 nsec/div 20.000ns 62 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION DATA at the S/UNI-APEX simulates monotonic edges with 22 ohm serial resistor. If the temperature and supply voltage range generates a fast-strong performance of the I/O pad, the simulations will need a serial termination resistor. The DSLAM Core Card Reference Design [4], with RAM1 and RAM2 only, has no serial termination resistor, as we do not expect a fast-strong I/O performance on our card (central office and lab environment/temperature range). Designers are encouraged to evaluate the signal integrity for the full range of IBIS models, from slow-weak to fast-strong. 6.5 S/UNI-APEX - SSRAM Timing The S/UNI-APEX - SSRAM bus timing requires proper edge timing and valid signal correction. That can be derived form a simulation. The components are configured as shown in FIGURE 50, FIGURE 51, and FIGURE 52 (2 x 2 SSRAM) and timing is described in following sections. 6.5.1 S/UNI-APEX - SSRAM Edge Timing The timing simulation for ADDRESS / DATA needs edge delays derived from simulation. FIGURE 53 shows the zoomed edge delays. FIGURE 53. ADDRESS to SSRAM, strong/fast, weak/slow A ADDRESS from APEX to SSRAM, fast-strong, 22 ohm near APEX 3.5V 0.98 ns 1.33 ns 1.07 ns 1.46 ns 3 1 200 psec/div 1 500 psec/div B 3.5 V ADDRESS from APEX to SSRAM, slow-weak, no termination 2.35 ns 4.17 ns 500 mV/div 3 500 mV/div 0 0 -1.0V 0 ns 1.0 ns 1.62 ns 2 ns 1.47 ns 0.87 ns -1.0 V 0 ns 2.48 ns 3.59 ns 5 ns Graph A shows that the signal at SSRAM-1 (marked 1) is reaching logic low and high later than the SSRAM-3 (marked 3) placed further on the bus. This phenomenon is due to back-reflections and a wave on the rising/falling edges. The slow-weak signal is about the same for all SSRAMs. 63 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 54 and FIGURE 55 show edge timing for DATA from SSRAM at the S/UNI-APEX (with a 22 ohm serial termination). FIGURE 54. DATA from SSRAM-3 at the S/UNI-APEX A DATA from SSRAM-3, slowweak, 22 ohm near APEX 3.5 volts B DATA from SSRAM-3, fast-strong, 22 ohm near APEX 3.500 V 500 ps/div 500 mV/div 500 ps/div 500 mV/div 0.0 volts 0.0 volts -1.0 V 0.0 ns 0.98 ns 1.52 ns 0.54 ns -1.0 volts 1.35 ns 2.28 ns 5.0 ns 5.0 ns FIGURE 55. DATA from SSRAM-1 at the S/UNI-APEX A DATA from SSRAM-1, slowweak, 22 ohm near APEX 3.5 V B DATA from SSRAM-3, slowweak, 22 ohm near APEX 3.5 V 500 ps/div 500 mV/div 500 ps/div 500 mV/div 0.0 V 0.0 V -1.0 V 1.26 ns 2.69 ns 1.43 ns 5.0 ns -1.0 V 0 ns 0.93 ns 1.46 ns 5 ns FIGURE 56 show edge timing for DATA from the S/UNI-APEX at SSRAM-3 with a 22 ohm serial termination. FIGURE 56. DATA at SSRAM slow-weak and fast-strong with 22 ohm DATA from APEX to SSRAM, fast-strong, 22 ohm near APEX 3.5V 0.79 ns 1.09 ns 0.91 ns 1.12 ns 3 1 200 psec/div 1 500 psec/div A B DATA from APEX to SSRAM, slow-weak, 22 ohm near APEX 3.5 V 2.0 ns 3.67 ns 500 mV/div 3 500 mV/div 0 -1.0V 0 ns 0 -1.0 V 0.87 ns 1.37 ns 0.74 ns 1.16 ns 2 ns 0 ns 2.15 ns 2.83 ns 5 ns Edge delays are derived from the figures above. We are now ready to do timing on ADDRESS to SSRAM and DATA to S/UNI-APEX. 64 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 6.5.2 SSRAM Valid Signal Correction The AC timing for the SSRAM devices is specified with 30 pF and 50 ohm to 1.25 V. The logic threshold is set at 1.25 V. This differs from the S/UNI-APEX load model that is of a pure capacitive type with a logic threshold at 50 % of Vdd. Also, the SSRAM data sheet does not specify a different load for maximum and minimum propagation delay - it is completed in the S/UNI-APEX, where the maximum propagation delay is with 40 pF and the minimum propagation delay is with 0 pF. The minimum propagation delay is determined with SSRAM IBIS fast-strong loaded with 30 pF and 50 ohm to 1.25 V. This may be the worst case, however, unless timing is clearly stated in the data sheets with the minimum and maximum load, we decided to use that approach. FIGURE 57 shows the timing diagram and LineSim graphs for the SSRAM DATA output IBIS fast-strong. FIGURE 57. SSRAM DATA output IBIS-weak/slow with 30 pF/50 ohm 0ns 80MHz CLOCK 0 Propagation Delay at SSRAM 1.5 3.5V 3.37ns 8.0ns 4.5ns 6.25 4.5 0.84ns 10ns 13.2 ns 12.5 14.0 3.5V SSRAM, IBIS slow-weak, 30 pF, 50 ohm to 1.25 V 2.0V 1.25V SSRAM, IBIS fast-strong, 30 pF, 50 ohm to 1.25 V 2.0V 0.8V 0 -1.0V 0 0 -1.0V 0 1.13ns 500 psec/div 500 mV/div 5 ns 0.80 ns 500 psec/div 500 mV/div 5 ns The SSRAM IBIS models slow-weak and fast-strong have the artificial digital reference points at 3.37 ns and 13.20 ns. This means the adjusted (artificial) propagation delay for the SSRAM is from 0.7 ns to 3.37 ns. Bus timing is determined using that adjusted propagation delay, plus the delay from I/O, and signal propagation over a copper trace. 6.5.3 Timing Diagram for 2 x 2 SSRAM Configuration FIGURE 58 shows the results of the timing correction values that are entered into the timing diagram. The timing is done with no termination on the ADDRESS line and with a 22 ohm serial termination on the DATA bus. 65 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 58. S/UNI-APEX to SSRAM-1 with IBIS slow-weak at 80 MHz 0ns 5ns 10ns 15ns 80 MHz CLOCK at APEX 0 1.5 1.5 6.25 12.5 ADDRESS to SSRAM-1 Data-sheet valid Address at APEX 8.25 14 3.52 Artificial Digital Valid Address, 40pF 1.18 4.73 4.17 Slow-weak Simulated Address arriving at SSRAM-1 Setup/Hold time at SSRAM-1 3.53 8.9 8.9 10.9 4.63 Slow-weak Valid Address window at SSRAM-1 10.9 1.6 CLOCK at SSRAM-1 0 0.32 13.68 2.35 16.03 15.53 3.03 CLOCK at SSRAM-1 0 DATA to APEX Datasheet 100MHz PipeLine SSRAM Read Data 1.5 4.5 1.13 3.37 2.69 6.06 14 0.8 13.2 1.26 14.46 0 36 Artificial Digital Valid Data from SSRAM Slow-weak Data from SSRAM-1 at APEX 1.96 Setup/Hold Time at APEX 6.06 2.4 8.46 5.3 Guarantied Valid Data Read at APEX 8.46 4.04 13.76 1.26 12.5 CLOCK at APEX" 0 CLOCK at APEX" 0 1.5 3.52 4.73 3.67 8.25 12.5 14 0.32 13.68 2 8.4 8.4 10.4 2.68 2.1 15.68 DATA to SSRAM-1 Valid Data output at APEX Artificial Digital Valid Data at APEX, 40pF 1.18 Slow-weak Data from APEX at SSRAM-1 Setup/Hold time at SSRAM-1' 3.18 CLOCK at SSRAM-1' 0 66 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 59 shows the S/UNI-APEX - SSRAM fast-strong timing. FIGURE 59. S/UNI-APEX to SSRAM-1 with IBIS Fast-strong at 80 MHz 0ns 5ns 10ns 15ns ADDRESS to SSRAM-1 80 MHz CLOCK at APEX 0 1.5 1.5 6.25 12.5 Datasheet valid Address at APEX, 40pF at 50 % 8.25 3.52 4.73 1.62 6.35 6.35 8.35 5.7 14 0.32 13.68 0.87 14.55 Artificial Digital Valid Address 1.18 Fast-strong simulated Address arriving at SSRAM-1 Setup/Hold time at SSRAM-1 2.05 Valid Address window at SSRAM-1 8.35 4.15 14.05 1.55 CLOCK at SSRAM-1 0 DATA to APEX CLOCK at SSRAM-1 0 1.5 4.5 1.13 3.37 1.46 4.83 14 0.8 13.2 0.93 14.13 0 0.7 Datasheet 100MHz PipeLine SSRAM Read Data Artificial Digital Valid Data from SSRAM 0.7 Fast-strong Data from SSRAM-1 at APEX 1.63 Setup/Hold Time at APEX 4.83 2.4 7.23 6.2 Guarantied Valid Data Read at APEX 7.23 5.27 13.43 0.93 12.5 CLOCK at APEX" 0 DATA to SSRAM-1 Datasheet Valid Data output at APEX, with 40 pF at 50 % 1.5 3.52 4.73 1.37 6.1 6.1 8.1 4.4 CLOCK at SSRAM-1' 0 1.42 8.25 14 0.32 13.68 0.74 14.42 Artificial Digital Valid Data at APEX 1.18 Fast-strong Data from APEX at SSRAM-1 Setup/Hold time at SSRAM-1' 1.92 67 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 6.5.4 Timing Summary for 2 x 2 SSRAM Configuration FIGURE 60 shows the summary of the timing diagrams shown in 0 and in FIGURE 59. This applies to the 2 x 2 SSRAM offset configuration. FIGURE 60. Timing Summary for SSRAM-1 with IBIS slow - fast 0ns 5ns 10ns 15ns 80 M H z C LO C K at A P E X 0 6.25 12.5 4.63 S low -weak V alid A D D R E S S at S S R A M -1 10.9 1.6 15.53 3.03 80 M H z C LO C K at S S R A M -1 0 5.3 S low -weak V alid D A T A from S S R A M -1 at A P E X 8.46 4.04 80 M H z C LO C K at A P E X" 0 12.5 13.76 1.26 S low -weak V alid D A T A from A P E X at S S R A M-1' 10.4 2.68 2.1 80 M H z C LO C K at S S R A M -1' 0 5.7 Fast-strong V alid A D D R E S S at S S R A M -1 8.35 4.15 80 M H z C LO C K at S S R A M -1 0 14.05 1.55 6.2 Fast-strong V alid D A T A from S S R A M -1at A P E X 7.23 5.27 80 M H z C LO C K at A P E X" 0 13.43 0.93 12.5 Fast-strong V alid D A T A from A P E X at S S R A M-1' 8.1 4.4 1.42 80 M H z C LO C K at S S R A M -1' 0 The timing above shows only the valid data or address sequence after subtracting the setup and hold time. The timing chart is based on signal simulation and corrected data sheet timing for the S/UNI-APEX. The SSRAM1 interface shows appropriate margins at weak/slow and strong/fast simulations. The smallest margin, 0.93 ns, is at the bottom of the drawing with timing named 68 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION "Fast-strong Valid DATA from SSRAM-1 at APEX". Other timing diagrams show at least 1.26 ns margins. It is important to observe that the above timing calculations do not include any clock edge degradation, such as: clock skew, jitter, and power/ground noise. Also, the clock is timed as a perfect transition. In a real circuit, the TTL level transition from 0.8 V to 2.0 V on a clock edge can be as long as 2 ns, which significantly decreases timing margins. Power noise and crosstalk is not included in timing simulation. FIGURE 61 and FIGURE 62 show examples of measured waveforms. IMPORTANT NOTE: The waveforms are obtained with a circuit limited to two ZBT SSRAM chips. This circuit is shown in the DSLAM Core Card Reference Design document [4]. FIGURE 61 shows a read from the SSRAM to the S/UNI-APEX. FIGURE 61. Waveforms at S/UNI-APEX at 80 MHz A B Graphs A and B show curves that are derived through the accumulation of ten consecutive reads from the ZBT SSRAM. The signal integrity is appropriate for this interface. The timing margin, shown in graph B, at 2.32 ns, leaves plenty of room for a 0.7 ns hold time that is specified in the S/UNI-APEX data sheets. 69 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 62 shows a write from the S/UNI-APEX to SSRAM. FIGURE 62. Waveforms at ZBT SSRAM at 80 MHz A B Graphs A and B show curves that are derived through the accumulation of ten consecutive writes to the ZBT SSRAM. The signal integrity, compared with the previous graphs, shows higher overshoots on the data lines CMD<0>. This is due to a lower current and higher speed delivered by the S/UNI-APEX I/O drivers. The signal integrity can be tested by using different serial termination resistors. The current design uses 22 ohm resistors. The timing margin, which is at about 2 ns and shown on graph B, leaves plenty of room for a 0.5 ns hold time that is specified in the GSI ZBT SSRAM data sheets. The clock in FIGURE 62 graph B is more "rounded" then in FIGURE 61 graph B, as it drives two RAM clock pins. The faster edges can be generated using separate drivers connected to each clock input. Separate drivers may introduce an edge skew. 6.6 S/UNI-APEX - SDRAM Interface The S/UNI-APEX to SDRAM signal integrity and timing margin calculation is not shown in this document. It can be completed in the same way as it is completed for the ZBT SSRAM interface. Preliminary simulation shows some signal degradation and a need for serial termination resistors as shown in the figures below. FIGURE 63 shows the signal integrity simulation for the S/UNI-APEX ADDRESS to the SDRAM. 70 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 63. ADDRESS to SDRAM APEX A APEX_pc3b02, ADDRESS at SDRAM, strong/fast, typical, no termination Address Bus B 10 APEX_pc3b02, ADDRESS at SDRAM, strong/fast, typical, 10ohm 3.500 volts 3.350 volts 500 mV/div 0.0 volts SDRAM 1 SDRAM 2 DATA Bus ADDRESS Bus 500 mV/div 0.0 volts -1.000 volts 0.000ns 2 nsec/div 20.000ns -1.150 volts 0.000ns 2 nsec/div 20.000ns APEX C 3.350 volts APEX_pc3b02, ADDRESS at SDRAM, strong/fast, typical, no termination D Address Bus APEX_pc3b02, ADDRESS at SDRAM, strong/fast, typical, 22ohm 3.500 volts 22 DATA Bus 0 SDRAM 1 SDRAM 2 500 mV/div 500 mV/div 0.0 volts ADDRESS Bus -1.150 volts 0.000ns 2 nsec/div 20.000ns -1.000 volts 0.000ns 2 nsec/div 20.000ns The difference between the upper and lower drawings is in the copper trace shape that connects the ADDRESS to the SDRAMs, and resistor values. Reference Design Core Card Issue 3 has address lines CBA[11:0] connected as shown in lower drawing. 71 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 64. DATA to/from SDRAM APEX_pc3b02, DATA at SDRAM, strong and typical 3.500 volts APEX DATA Bus 500 mV/div 0.0 volts -1.000 volts 0.000ns 2 nsec/div 20.000ns DATA from SDRAM at APEX, strong-typical-slow ADDRESS Bus SDRAM 1 SDRAM 2 DATA Bus 3.500 volts 500 mV/div 0.0 volts -1.000 volts 0.000ns 2 nsec/div 20.000ns The DATA bus in both directions simulates monotonic edges across the transition region, 0.8 V to 2.0 V, with some margins above and below those logic levels. The MOSEL SDRAM IBIS model outputs a different peak voltage depending on the "weak-typical-strong" option. The S/UNI-APEX model it is always at 3.3 V. This is due to the IBIS model differences, where the MOSEL SDRAM uses a more accurate parameter called [Rising Waveform], which cannot be simulated at the present time with the S/UNI-APEX model. The expected difference is estimated at about two hundred ps, and it should not cause major upsets in real bus timing. 72 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION The figures below show examples of measured waveforms. FIGURE 66 shows a write to SDRAM from the S/UNI-APEX. FIGURE 65. Waveforms at SDRAM at 80 MHz The trace descriptions (next to the right edge of the above graph) apply to the SDRAM pinout shown on the Core Card SDRAM schematics (document [4]). The clock signal is not shown in the figure above. The oscilloscope captures digital signals that show sixteen consecutive write cycles to the SDRAM executed by the S/UNI-APEX. The DQ0 trace between 200 ns cursors shows the binary data pattern 1000000000000001 written to the SDRAM. 73 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 66 shows the zoomed pattern with clock and timing margins. FIGURE 66. Waveforms at SDRAM at 80 MHz The digital lines shown above are: * * * A0 - address to SDRAM D0 - data to SDRAM WEB - write enable to SDRAM. The oscilloscope is triggered with the WEB signal. The timing shows about a 2.9 ns margin that is enough for a 1.0 ns hold time for the 100 MHz SDRAM (as specified in the MicronTM data sheets). 74 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 67 shows the data flowing from the SDRAM to the S/UNI-APEX. FIGURE 67. Waveforms at the S/UNI-APEX at 80 MHz The digital line CBDQ<0> is the data at the S/UNI-APEX coming from the SDRAM. The clock at the S/UNI-APEX pin SYSCLK is abut 2.6 ns ahead of the data, leaving enough of a margin with a 0.7 ns hold time as specified in the S/UNI-APEX data sheets. 75 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 7 S/UNI-ATLAS/ and S/UNI-APEX UTOPIA L2 AND ANY-PHY BUS TIMING The S/UNI-ATLAS and the S/UNI-APEX timing on Utopia L2 and Any-PHY buses is presented in this section. The signal integrity simulation for the S/UNI-ATLAS, S/UNI-VORTEX, and S/UNI-DUPLEX are based on a preliminary IBIS typical model only. 7.1 S/UNI-ATLAS Timing Correction The S/UNI-ATLAS data sheet specified a propagation delay of 50 pF and 20 pF. This simulation is based on a 50 pF delay time. The RADDR[4..0] propagation delay is specified at 1 to 12 ns with 50 pF at 1.4 V. FIGURE 68 shows the pbct12 IBIS typical model plots. The clock frequency is 52 MHz, which is the maximum clock speed for the Utopia L2 bus. FIGURE 68. Adjusted Propagation Delay for pbct12 IBIS Typical 0 ns 10.07 ns 19.98ns 10 ns 9.62 19.23 12 2.5 ns 20 ns 52 MHz CLOCK Datasheet Propagation Delay at ATLAS 1.0 A 20.23 0.43 ns 3.5V B pob12, IBIS weak/slow, 50 pF load, 1.4 V 0 1.4 V -1.0 V 0 1.93 ns 500 psec/div 500 mV/div 5 ns 0 0.25 ns 500 psec/div 5ns IBIS typical, no load Graph A shows the IBIS pob12 pad loaded with 50 pF. The graph is aligned with a falling edge crossing point at 1.4 V with 12 ns mark on the time scale. The correction point is calculated at 10.07 ns. Graph B shows the IBIS typical unloaded pad aligned with 20.32 ns. This point is derived by adding one nanosecond to the clock period (20.23 ns = 1000/ (52 [MHz]) +1 = 19.23 + 1). The correction points for the S/UNI-ATLAS pob12 I/O pad are determined at 10.07 ns and 19.98 ns for the IBIS typical model. The very same performance is simulated for the S/UNI-VORTEX and the S/UNI-DUPLEX Utopia I/O pads (pbcst12). 76 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 7.2 UTOPIA L2 Timing with Offset Configuration After reviewing different configurations, it was decided to work on bus timing which simulates the most monotonic edges. Ttechnical literature points to data corruption with non-monotonic signals. The offset configuration, shown earlier in FIGURE 29 and FIGURE 30, was slightly modified by adding a serial resistor at the S/UNI-VORTEX-5. The simulation shows monotonic edges with very small bumps that should be acceptable in most applications. FIGURE 69 shows the bus configuration and signal edges for RADDR[4..0] and RRDENB. FIGURE 69. Modified In-line Configuration and Edge Timing VORTEX 9 VORTEX 5 VORTEX 1 Offset configuration; 11 inputs VORTEX 10 VORTEX 6 33 ATLAS VORTEX 4 33 DUPLEX Controlled impedance bus (~50ohm) ATLAS driver ATLAS to VORTEX-10, 2x33 ohm and 33 ohm at VORTEX-5 3.500 volts ATLAS to VORTEX-5, 2x33 ohm and 33 ohm at VORTEX-5 3.500 volts 500 mV/div 500 mV/div 0.0 volts 0.0 volts -1.000 volts 0.000ns 5 nsec/div 50.000ns -1.000 volts 0.000ns 5 nsec/div 50.000ns ATLAS to VORTEX-5, 2x33 ohm and 33 ohm at VORTEX-5 3.500 volts 4.37 ns 7.04 ns 1 nsec/div 500 mV/div 0 -1.0 V 0 2.37 ns 7.37 ns 10 ns FIGURE 70 shows the simulation that applies to the RDAT[15..0], RCA, RPRTY and RSOC bus signals. 77 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 70. In-line Configuration and Edge Timing VORTEX-9 VORTEX-5 VORTEX-1 Offset configuration; 11 outputs VORTEX-10 DUPLEX Controlled impedance bus (~50ohm) 68 ATLAS ATLAS receiver VORTEX-10 to ATLAS, "typical", 68 ohm at T 3.500 volts VORTEX-5 to ATLAS, "typical", 68 ohm at T 3.500 volts 500 mV/div 500 mV/div 0.0 volts 0.0 volts -1.000 volts 0.000ns 5 nsec/div 50.000ns -1.000 volts 0.000ns 5 nsec/div 50.000ns VORTEX-10 to ATLAS, typical, 68 ohm at T 3.500 volts 4.67 ns 7.59 ns VORTEX-5 to ATLAS, typical, 68 ohm at T 3.500 volts 5.15 ns 8.59 ns 1 nsec/div 500 mV/div 1 nsec/div 500 mV/div 0.0 volts 0 -1.000 volts 0.000ns 3.96 ns 7.85 ns 10 ns -1.0 V 0 4.48 ns 8.96 ns 10 ns 78 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 7.3 Clock Propagation Timing in Offset Configuration The clock propagation delay along copper traces is determined in the offset configuration (as shown in FIGURE 69). FIGURE 71 show the delays. FIGURE 71. CLOCK Propagation Delays with Offset Configuration VORTEX9 VORTEX1 DUPLEX VORTEX10 CLOCK3 DATA/ADDRESS B t=2.62 ns t=1.46 ns Clock Driver CLOCK1 CLOCK2 1.12 ns 6.27" DATA/ADDRESS 1.60 ns 8.9" A C ATLAS/ APEX Total CLOCK1 delay = 1.60 ns Total CLOCK2 delay 1.46 + 1.12 = 2.58 ns Total CLOCK3 delay = 2.62 ns The clocking is referred to an idealized CLOCK0. CLOCK1 from A to the S/UNIVORTEX-1 at B travels in 1.60 ns. CLOCK2 from A to C is set to have the delay at 2.58 ns, which consists of line A to C with a delay of 1.12 ns (6.44 inches long) and an additional skew of 1.46 ns. CLOCK3 from A to S/UNI-VORTEX-10 is the shortest distance, and it has inserted a delay at 2.62 ns. Those values are entered later in the timing diagram in FIGURE 72. The delays through buffers and on copper traces are critical for clocking the ADDRESS and DATA on the Utopia bus. As it is shown above and in the timing diagram, the clock edge skew at the destination does not need to be 0.0 ns (zero ns) for the best timing performance. The optimal clock skew depends on the signal integrity. To simplify, the clock is timed as it would be an ideal square wave. An edge distortion may affect the physical board timing. The signal integrity simulation is not used for clock propagation and timing. All ingredients needed for the bus timing are now derived through the signal integrity simulation (done earlier in this document) and through the copper trace propagation timing (above). FIGURE 72 shows the bus timing simulation that can be done now. 79 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 72. UTOPIA L2 Bus "typical" ADDRESS and DATA at 52MHz 0ns 10ns 20ns CLOCK 0 CLOCK2 at ATLAS 2.58 1 12 Data-sheet-valid RADDR[4..0] at ATLAS 3.58 (-0.25) 3.33 3.59 RADDR[4..0] at VORTEX-10 6.92 14.58 (-1.93) 12.65 7.93 20.58 0 Setup/hold time for VORTEX 3 20.58 23.58 21.81 1 22.81 (-0.25) 22.56 3.59 26.15 Adjusted valid RADDR[4..0] at ATLAS 0 (-1) 26.15 0 25.15 0 1.57 Valid RADDR[4..0] window at VORTEX-10 23.58 -1.73 CLOCK3 at VORTEX-10' CLOCK 0' CLOCK3 at VORTEX-10" 2.62 2 12 Datasheet output RDAT[15..0] at VORTEX 4.62 (-0.25) 4.37 3.96 RDAT[15..0] arriving at ATLAS 8.33 14.62 (-1.93) 12.69 7.85 20.54 0 Setup/hold time for ATLAS 3 20.54 23.54 0 23.54 0 (-1) 27.56 0 26.56 2 23.85 (-0.25) 23.6 3.96 12.24 2.62 19.23 21.85 21.85 Adjusted valid RDAT[15..0] at VORTEX Valid RDAT[15..0] window at ATLAS -1.73 CLOCK2 to ATLAS' 2.58 21.81 The S/UNI-ATLAS to/from S/UNI-VORTEX-10 valid ADDRESS and DATA misses clock with 1.73 ns on setup time. The equal delay on both timings is achieved 80 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION through adjusting the clock delay at the S/UNI-APEX and at the S/UNI-VORTEX10. The clock skew is 2.62 - 2.58 = 0.08 ns. The saw-tooth distortion of the signal is the main reason why the timing margin failed on setup time. Graph A in FIGURE 73 shows the square wave on an unloaded output with the saw-tooth signal. FIGURE 73. DATA and Clock Edge Distortion A VORTEX-10 to ATLAS, "typical", 68 ohm at T 3.5 V 3.500 volts B CLOCK edge 500 mV/div 500 mV/div 0.25ns 0.25ns 0 0.0 volts -1.0 V0 T = 5.5 ns 5 nsec/div 50 ns -1.000 volts 0.000ns 500 psec/div 5.000ns The edge-distorted signal loses about 5.5 ns, if it is compared to an idealized square wave. The Utopia bus with ten S/UNI-VORTEX devices, one S/UNIDUPLEX device, and one S/UNI-ATLAS device cannot simulate a square wave. and therefore, the bus cannot run at 52 MHz. The clock edge transition time is not included in the timing above. The clock edge, shown in FIGURE 73 graph B, has a transition time of about 0.25 ns. This may further decrease the margins in the analyzed timings. The obvious solutions it to slow down the clock. (or violate rules and pray it works ). The clock frequency is recalculated as follows: 19.23 Fnew = 52 19.23+1.73 = 46.59 MHz, 19.23 ns is the clock period at 52 MHz. 1.73 ns is the timing violation from FIGURE 72. At the frequency of 46.59 MHz the clock edge will be exactly at the beginning of the valid data window, as shown in FIGURE 72. If the hold time would be violated, then slowing down the clock may not help. The hold time violation can be improved by increasing the device minimum propagation time (for example, from 2 ns to 3 ns) and decreasing the hold time at 81 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION receiving device (for example, from 1 ns to 0.5 ns), which is impossible as those parameters are embedded into the silicone. The timing simulation process shown above has to be repeated for all combinations of the S/UNI-ATLAS, S/UNI-VORTEX, S/UNI-DUPLEX, ADDRESS, and DATA. We recommend that you check the performance with the IBIS model set at "weak/slow" and "strong/fast". There are numerous permutations and simulations. The data sheet timing, as shown in FIGURE 39 and FIGURE 40, shows zero or very little margin on the hold time, and our exercise shows a violation on the setup time - what can be summarized as ... surprise, surprise!!!. We had received numerous questions about hold time near-violation (0.0 ns margin) as shown in FIGURE 39 and FIGURE 40. The above exercise highlights need for signal integrity simulation, and timing simulation based on signal integrity. If that is not done, unexpected timing violations may show up on a board, which might be prevented if signal simulations are done to pre-layout (and post-layout circuit, but before making PCB). 7.4 S/UNI-APEX Timing 7.4.1 S/UNI-APEX Timing Correction The S/UNI-APEX timing on the Any-PHY bus is derived in the same way as the S/UNI-APEX - RAM timing described in the previous sections. The data sheet specifies the propagation delay TPLCLK at 1.75 ns to 10 ns with 80 pF load at 50 %. The Any-PHY I/O timing is different from the RAM interface timing, and therefore correction parameters have to be recalculated. FIGURE 74 shows the digital and I/O delays at 52 MHz. 82 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 74. Propagation Delay for pc3b04 IBIS slow-weak with 80 pF 0 ns 80 MHz CLOCK Datasheet Propagation Delay at APEX 1.75 A 3.5 V 5.44 ns 10 ns 20.66 ns 10 ns T = 4.56 ns 9.62 10 B 19.23 20 ns 20.98 3.5V pc3b04, IBIS-weak/slow, 80 pF load 0 1.65 V pc3b04, IBIS fast-strong, no load 2.0V 0.8V 0 -1.0 V 0 500 psec/div 500 mV/div 5 ns -1.0V 0.27 ns 4.56 ns 0.32 ns 5ns The LineSim graph A is positioned in such a way that the pc3b04 slow-weak IBIS model loaded with 80 pF crosses 1.65 V (50 %) at the 10.0 ns mark at the timing bar. The LineSim tool starts the simulation process at about the 5.44 ns mark. This means the digital delay must not exceed 5.44 ns. Graph B shows the unloaded falling and rising edges at fast-strong. This graph is positioned in such a way that the edge at 1.65 V is aligned with the 20.98 ns mark on the timing diagram, setting the 20.66 ns point. The 5.44 ns and 20.66 ns marks are artificially created start points for LineSim edge that travels along bus line. Those points and time differences (0.32 ns and 4.56 ns) are also entered into timing diagrams (shown later in this document). 7.4.2 S/UNI-APEX Driving Offset Bus with Multiple Termination The S/UNI-APEX I/O pad pc3b04 differs from the S/UNI-ATLAS I/O in speed and current, and therefore creates different back-reflection patterns. FIGURE 75 shows edge distortions. 83 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION FIGURE 75. Edge Distortion Delay VORTEX 9 VORTEX 5 VORTEX 1 Offset configuration; 10 inputs VORTEX 10 DUPLEX Controlled impedance bus (~50ohm) 33 APEX 33 APEX driver APEX to VORTEX-10, 2x33 ohm and 33 ohm at VORTEX-5 3.500 volts APEX to VORTEX-5, 2x33 ohm and 33 ohm at VORTEX-5 3.500 volts APEX to VORTEX-6, 2x33 ohm and 33 ohm at VORTEX-5 3.500 volts 500 mV/div 500 mV/div 500 mV/div 0.0 volts 0.0 volts 0.0 volts -1.000 volts 0.000ns 5 nsec/div 50.000ns -1.000 volts 0.000ns 5 nsec/div 50.000ns -1.000 volts 0.000ns 5 nsec/div 50.000ns APEX to VORTEX-10, 2x33 ohm and 33 ohm at VORTEX-5 3.500 volts 4.44 ns 7.67 ns 3.500 volts APEX to VORTEX-5, 2x33 ohm and 33 ohm at VORTEX-5 4.82 ns 6.93 ns 3.500 volts APEX to VORTEX-6, 2x33 ohm and 33 ohm at VORTEX-5 3.70 ns 5.96 ns 1 nsec/div 500 mV/div 1 nsec/div 500 mV/div 1 nsec/div 500 mV/div 0.0 volts 0 0 -1.000 volts 0.000ns 3.93 ns 8.70 ns 10 ns -1.0 V 0 3.26 ns 8.78 ns -1.0 V 10 ns 0 2.00 ns 6.15 ns 10 ns The signal edges at S/UNI-VORTEX-6 show multiple back-reflections. The only solution is to add a serial resistor at the S/UNI-VORTEX-6 (and maybe the S/UNI-VORTEX-7), and that will simulate similar to the signal at the S/UNIVORTEX-5. The total number of resistors for each bus will increase to four, and that may not be a realistic solution. There is no guarantee that, even with four resistors, the bus can run at 52 MHz. The edge-distorted signal, from the S/UNI-APEX to the Any-PHY bus, may prevent the building of the Any-PHY bus size. The pc3b04 I/O pad cannot deliver the required signal to simulate the low distorted monotonic edges with the given bus size. Clock edge transition, jitter, and skew further deteriorate timing 84 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION margins. However, to close this exercise, bus timing is simulated and shown below. FIGURE 76 shows how the Any-PHY bus timing. FIGURE 76. Any-PHY Bus Timing Simulation at 52 MHz 85 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 0ns 10ns 20ns CLOCK 0 CLOCK2 at APEX 2.58 1.75 10 Data-sheet-valid LTADR[11..0] at APEX 4.33 (-0.32) 4.01 3.93 LTADR[11..0] at VORTEX-10 7.94 (-4.56) 8.02 8.78 16.72 0 Setup/hold time for VORTEX 3 16.72 19.72 26.42 0 5.7 Valid LTADR[11..0] window at VORTEX-10 19.72 0 25.42 12.58 1 22.81 (-0.32) 22.49 3.93 26.42 21.81 Adjusted valid LTADR[11..0] at APEX 0 (-1) -0.3 CLOCK3 at VORTEX-10' CLOCK 0' CLOCK3 at VORTEX-10" 0.19 2 12 Data-sheet output TDAT[15..0] at VORTEX 2.19 (-0.25) 1.94 3.96 TDAT[15..0] arriving at APEX 5.9 12.19 (-1.93) 10.26 7.85 18.11 0 Setup/hold time for APEX 4 18.11 22.11 0 22.11 2 21.42 (-0.25) 21.17 3.96 25.13 0 0 25.13 0 25.13 9.81 0.19 19.42 19.23 19.42 Adjusted valid TDAT[15..0] at VORTEX Valid TDAT[15..0] window at APEX -0.3 CLOCK2 to APEX' 2.58 21.81 The S/UNI-APEX - S/UNI-VORTEX-10 valid ADDRESS and DATA misses the clock with 0.3 ns on setup time. The equal delays on both timing charts are achieved through adjusting the clock delay at the S/UNI-APEX and at the S/UNIVORTEX-10. The clock skew is 2.58 - 0.19 = 2.39 ns. 86 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION Similar to the previous Utopia L2 bus simulation, the saw-tooth distortion of the signal is the main reason for setup time failure. The clock frequency, allowing setup at 0.0 ns margin, can be calculated at: 19.23 Fnew = 52 19.23+0.3 = 51.20 MHz, 19.23 ns is the clock period at 52 MHz. 0.3 ns is the timing violation from FIGURE 76. At 51.20 MHz frequency, the clock edge will be exactly at the beginning of the valid data window, as shown in FIGURE 76. 87 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 8 8.1 VORTEX CHIPSET SIMULATION SUMMARY Simulation Tools Three CAD tools have been evaluated for the bus simulation project: SpecctraQuest and LineSim for the pre-layout signal integrity simulation, and TimingDesigner - Professional 32 for bus timing simulation. LineSim is a relatively low cost CAD tool, suitable for pre-layout simulation in an applications environment. Its advantage over the UNIX-based SpecctraQuest is its easy installation in a Win95/98/2000 environment, its click-and-build simulation circuit, and its easy transfer of the simulation results (graphs) into MSWord documents. Minor deficiencies do exist and may frustrate its user. TimingDesigner - Professional 32 was only evaluated for graphical representation of timing derived from signal integrity. The tool provided adequate functionality for this exercise. 8.2 In-line Configuration DUPLEX/VORTEX 11 1 The in-line configuration with the central connection to the S/UNIATLAS and the S/UNI-APEX is APEX/ATLAS more preferable over the bus-end connection. The address and data from the S/UNI-ATLAS/S/UNIAPEX shows a strong saw-tooth shape, non-monotonic edges near the bus center, and rounded edges near the bus-end. S/UNI-APEX to S/UNI- 0ns 5 nsec/div 500 mV/div 50n The S/UNI-VORTEX/S/UNIDUPLEX to S/UNI-ATLAS/S/UNIAPEX in the bus-center connection shows a saw-tooth distortion. The serial termination resistor is required at the T joint to the S/UNIATLAS/S/UNI-APEX. 68 termination Vortex-5 to ATLAS-2 11 DUPLEX/VORTEX 1 APEX/ATLAS 0ns 5 nsec/div 50n 88 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION The bus-center configuration, going from the S/UNI-APEX/S/UNI-ATLAS towards the bus, is significantly improved if an additional high-speed buffer is inserted. The bus is split into three sub-sections. However, you need six 16-bit drivers, and the bus line count goes from 31 to 93. Buffer propagation delay and skew may "kill" bus timing. 11 DUPLEX/VORTEX 1 3.5V APEX to VORTEX 6 BUFFER APEX/ATLAS 0V -1.0V 0ns 5 nsec/div 500 mV/div 50n The S/UNI-ATLAS/S/UNI-APEX at the bus-end is not suitable as the simulated signal shows a very long edge-shelf. 11 DUPLEX/VORTEX 1 3.5V VORTEX-11 to ATLAS APEX/ATLAS 0V -1.0V 0ns 5 nsec/div 500 mV/div 50n The S/UNI-APEX at the bus-end may work with a high-current high-speed buffer. Also, high impedance traces, at least Zo=100 ohm, with termination resistors at the bus ends are required. High Zo traces are difficult for PCB layout and manufacture. The TPA line goes towards the S/UNI-APEX on the bus, and simulation shows a long shelf from the S/UNI-VORTEX devices, near the beginning of the bus, making it impossible to clock the data. 11 DUPLEX/VORTEX VORTEX-10 1 3.5V Hi-current Hi-speed BUFFER APEX/ATLAS 0V -1.0V 0ns 5 nsec/div 500 mV/div 50n TPA from VORTEX-10 11 DUPLEX/VORTEX 1 3.5V TPA=? APEX 0V -1.0V 0ns 5 nsec/div 500 mV/div 50n ? 89 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 8.3 Offset Configuration The offset configuration naturally supports central connection of the S/UNI-ATLAS and the S/UNI-APEX. The bus is split into two subsections to ease the Receive/Transmit ports connection. The simulated signal in the Receive Data direction shows slow rising/falling edges that add delays to the timing simulation. DUPLEX to ATLAS DUPLEX/VORTEX 11 1 APEX/ATLAS 0ns 5 nsec/div 500 mV/div 50n The Transmit Data direction shows relatively high distortions and difficulties to terminate transmission lines. ATLAS/APEX to a bus DUPLEX/VORTEX 11 1 APEX/ATLAS 0ns 5 nsec/div 500 mV/div 50n The offset configuration with a single bus simulates a slightly better signal on the far ends of the bus. However, the center of the bus shows the non-monotonic edges. Multiple termination resistors are needed across the bus. The Receive Data direction simulates a signal similar to the double offset bus shown on the previous page. APEX to VORTEX-6 DUPLEX/VORTEX 11 1 APEX/ATLAS 0ns 5 nsec/div 500 mV/div 50n 90 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 8.4 S/UNI-APEX-RAM Interface The S/UNI-APEX RAM interface was simulated with the IBIS model options set to weak/slow and strong/fast. APEX to 8 SSRAMs, center connection to asymmetric bus at 80MHz The S/UNI-APEX cannot provide an interface with four/eight SSRAM devices connected at 80 MHz, as shown here . SSRAM SSRAM 3.5V APEX APEX 0 -1.0V 0 2 nsec/div 500 mV/div 20ns APEX to 4 SSRAMs at 80MHz The S/UNI-APEX can provide an interface with two/four SSRAM devices connected at 80 MHz, as shown here. SSRAM 3.5V APEX 0 -1.0V 0 2 nsec/div 500 mV/div 20ns 8.5 Clock Signal Integrity To avoid non-monotonic edges in the logic transition window 0.8 to 2.0 V, the clock must be distributed with multiple lines. The buffer has to be chosen to provide IDT IDT74LVCH16244 This one was used for the DUPLEX/VORTEX 11 1 adequate speed and driving capacity. clock line simulation. 3.5V The clock lines need serial termination and/or Thevenin terminations to BUFFER IDT74LVCH16244 suppress overshoots and the high 500 mV/div CLOCK current through the clamping diodes, and in turn a "silicon" noise to 0.0 volts adjacent "quiet" I/O pads or electron -1.0V 0ns 2 nsec/div 20ns injection dipper into silicon. Silicone crosstalk applies to any bus lines with a high overshoot as well. 91 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION The fast and high current drivers may create EMI problems- that are not addressed in this document. A driver that is too fast (such as Philips 74ALVT16244) may cause problems with overshoots. 8.6 Bus Timing The S/UNI-APEX and S/UNI-ATLAS interface to Utopia L2 and Any-PHY bus is simulated in this document using the IBIS "slow-weak" model. Single Bus Offset Placement Configuration The timing simulation, shown in FIGURE 72, with the S/UNI-ATLAS, ten S/UNI-VORTEX devices, and the S/UNI-DUPLEX on a Utopia L2 bus calculates a 1.73 ns setup violation with the clock at 52 MHz. Clock at about 46 MHz works. Valid Data 21.85 23.58 -1.73 52 MHz 46.59 MHz Valid Data 19.42 19.72 -0.30 The timing simulation shown in FIGURE 72 52 MHz with the S/UNI-APEX and ten S/UNI51.20 MHz VORTEX devices on an Any-PHY bus calculates a 0.30 ns setup violation with the clock at 52 MHz. Slowing down the clock helps to eliminate setup time violations. Possible timing improvements can be done by: improving signal integrity on the bus, which is the most important (one suggestion may be to add multiple serial terminating resistors); decreasing physical size and trace length on the bus; decreasing the number of devices connected to the bus; slowing down the clock (helps with setup time violations) 92 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 8.7 Future Simulations We need to investigate simulations based on signal integrity with a data sheet correction approach to bus timing. We must question: * Is timing simulation based on signal integrity and adjusted data sheet timing correct? What can be done to bring simulation closer to the measured signal integrity on tested boards? * A need for additional simulations was pointed throughout this document. We need to investigate the following possible directions: * Improve signal integrity and eliminate the saw-tooth delay, which kills timing at 52 MHz. Place components in closer proximity to decrease the overall bus dimension. Place components double sided (some RAM manufacturers are introducing double sided footprints). Place less devices on the bus simulation; Compare signal integrity simulation done with HyperLynx against other simulation tools. Verify simulations presented throughout this document on a built and tested boards. * * * * * 93 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 9 DISCLAIMER This document is based on hands-on experience with simulation tools and is an unconventional interpretation of the data sheet AC timing. In the author's opinion, the data sheet AC timing (for any silicone device throughout the silicone industry) cannot be directly used for signal integrity and timing simulation. The proposed method of timing calculation, based on signal integrity and an artificially created starting point for the IBIS model, needs further investigation and comparison with built and tested large Utopia and Any-Phy buses. Simulation results are general direction pointers, which may not prove or disprove bus timing and signal integrity. It is always required to verify simulated results. However, simulation tools utilized for pre-layout simulations can capture timing violations and signal integrity problems preventing a major disappointment when assembled board, with a large bus, experience soft errors due to bus signal irregularities. PMC-Sierra does not approve, disapprove, or recommend any CAD or simulation tools. 94 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION 10 GLOSSARY Any-PHY IBIS I/O S/UNI BGA DSLAM PCB PMC-Sierra proprietary ATM cell size with a 2-byte prepend Input/Output Buffer Information Specification Input/Output Saturn User Network Interface Development Group Ball Grid Array Digital Subscriber Line Access Multiplexer Printed Circuit Board 95 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED DSLAM APPS NOTE PMC-1990816 ISSUE 1 VORTEX CHIPSET SIGNAL INTEGRITY AND TIMING SIMULATION PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com Document Information: Corporate Information: Applications Information: Web Site: None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2000 PMC-Sierra, Inc. PMC-1990816 (R1) Issue date: November 2000 PMC-SIERRA, INC. 105 - 8555 BAXTER PLACE BURNABY, BC CANADA V5A 4V7 604 .415.6000 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE |
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